dtj v02-04 1990

This issue of the Digital Technical Journal, Volume 2, Number 4 (Fall 1990), is entirely dedicated to the Digital Equipment Corporation (DEC) VAX 9000 Series mainframe/supercomputer, which was introduced in Fall 1989. The document highlights the extensive technical innovations and design strategies employed to achieve high performance and reliability for this complex system.

The key aspects covered include:

1. Design Strategy: The VAX 9000's performance was achieved by applying Reduced Instruction Set Computer (RISC) concepts to the Complex Instruction Set Computer (CISC) VAX architecture. This involved breaking VAX instructions into smaller, pipelined tasks, allowing for concurrent operation and an execution rate of one simple VAX instruction per clock period (16 nanoseconds). This strategy involved redesigning the CPU (I-box, E-box, M-box) to overlap operations, implement operand prefetching, and enhance branch prediction.

2. Semiconductor Technology: The system utilizes a new generation of high-performance bipolar integrated circuits, specifically Motorola's Macrocell Array III (MCA3) for gate arrays, custom chips for critical operations (multiplication, division, vector register access), and proprietary self-timed RAMs (STRAMs) for fast local storage.

3. Vector Processing: An optional, integrated vector processor (V-box) significantly boosts performance for numerically intensive applications (4-5 times over scalar performance). It features a unique vector register file design, allowing up to three vector instructions to overlap execution, and supports random-strided memory access, compressed IOTA vectors, and vector register merging.

4. Packaging and Interconnects: To ensure performance gains from semiconductors weren't lost, Digital developed unique High-Density Signal Carriers (HDSC) and Multichip Units (MCU). These technologies, incorporating tape automated bonding (TAB), reduced interconnect delays and provided efficient cooling for high-power chips.

5. Service Processor Unit (SPU): A dedicated, MicroVAX-based subsystem embedded within the VAX 9000 system handles real-time error detection, isolation, and correction without interrupting system operation. It also provides crucial debugging features for development and manufacturing through a system-wide scan architecture.

6. Power System Design: Emphasizing high availability, the power system incorporates features like N+1 redundancy for regulators, improved load sharing among parallel regulators, and strategic decoupling of major power system sections to allow maintenance without full system shutdown.

7. CAD Methodology & Fault Detection: The design process utilized a sophisticated Computer-Aided Design (CAD) system employing rule-based AI techniques and an object-oriented database for logic synthesis, placement, routing, and timing analysis. This was complemented by a hierarchical fault detection and isolation strategy, including a new scan system, scan pattern testing, and symptom-directed diagnosis (SDD) to swiftly identify and pinpoint failures.

In essence, the journal details how Digital achieved a high-performance, highly reliable, and compatible mainframe/supercomputer in the VAX 9000 by combining innovative architectural designs, cutting-edge semiconductor technology, advanced packaging, and comprehensive fault management and design automation tools.