dtj v01-07 aug1988

This Digital Technical Journal, Number 7, published in August 1988, focuses on CVAX-based Systems developed by Digital Equipment Corporation. The issue highlights the second generation of VLSI (Very Large Scale Integration) VAX chips, the new computer systems leveraging these chips, and the advancements in the VAX/VMS operating system to support symmetric multiprocessing.

The document primarily covers:

1. Overview of the VAX 6200 Family of Systems: This mid-range, high-performance, and expandable family utilizes a multiprocessing architecture (up to 4 CPUs, offering up to 11 times the performance of a VAX-11/780). It features a new high-speed shared-memory interconnect called the XMI bus (64-bit, 100MB/s bandwidth) and uses the VAXBI bus for I/O. Key design elements include hardware-maintained cache coherency, modularity, and extensive built-in self-tests.

2. MicroVAX 3500/3600 Processor Module: Described as a low-end system, it delivers three times the performance of its predecessor, the MicroVAX II, primarily through its CVAX-based uniprocessor and an unusual two-level cache architecture (a fast 1KB on-chip cache and a larger 64KB on-module cache).

3. The CVAX Chip Set: The high performance of both system families is largely attributed to this CMOS VAX chip set, which includes:

   • CVAX 78034 Chip (32-bit Microprocessor): The core CPU, which reduced "ticks per instruction" (TPI) by 27% and achieved an 80-90 nanosecond (ns) machine cycle time, contributing to its significant performance gains. It features an on-chip instruction/data stream cache and a translation buffer.
   • CVAX Floating Point Chip (CFPA): A coprocessor designed to provide floating-point performance comparable to the CVAX CPU's integer performance, achieving a three-fold speedup over the previous MicroVAX FPU through a multiplier array and improved arithmetic algorithms.
   • System Support Chip (SSC): A multifunction chip that integrates a common core of peripheral system functions such as timers, VAX console support, and standby RAM, reducing component count and simplifying system design.
   • CVAX Q22-bus Interface Chip (CQBIC): A highly integrated single chip that serves as the interface between the CVAX microprocessor and the Q22-bus I/O subsystem, featuring scatter-gather map cache and data buffering for optimized I/O performance.
   • CVAX CMCTL (CMOS Memory Controller Chip): An ECC (error-correcting code) memory controller for Q-bus-based systems, optimized for high-speed page-mode RAM access and supporting multi-word data transfers.

4. VMS Symmetric Multiprocessing (SMP): VMS version 5.0 introduces symmetric multiprocessing capabilities, allowing multiple CPUs to efficiently share a single operating system image. A key innovation is the use of "spinlocks" for kernel-mode code synchronization, providing finer granularity and greater parallelism than previous interrupt priority levels (IPLs).

5. Design and Verification Methodologies: The journal emphasizes the crucial role of Computer-Aided Engineering (CAE), extensive simulation, and rigorous verification plans in achieving the goal of first-pass functional hardware for these complex systems, significantly shortening the development cycle. Performance evaluation methodologies and results for both single-stream and multi-user workloads are also detailed, confirming the near-linear scalability and balanced nature of the VAX 6200 systems.

In essence, the document chronicles Digital's successful strategic shift to CMOS VLSI technology for its VAX systems, enabling higher performance, greater scalability through multiprocessing, and enhanced reliability, all while meeting aggressive development schedules.