VAX 8800 Family

This issue of the Digital Technical Journal details the design and development of Digital Equipment Corporation's VAX 8800 family of CPUs, comprising the VAX 8800, 8700, 8550, and 8500 systems. These processors offer a sustained applications throughput ranging from 3 to 12 times that of the VAX-11/780, achieved through a balanced, high-performance design.

Key aspects include:

• High Performance Architecture: A 45-nanosecond cycle time is achieved using ECL technology, a five-stage instruction execution pipeline, and integral floating-point acceleration.
• Key Components: The CPU design is segmented into logical "boxes": the I Box (instruction unit), C Box (cache), E Box (execution unit), and M Box (memory subsystem), connected by high-speed buses like the NMI (memory interconnect) and VAXBI (I/O) buses.
• Advanced Clock System: A two-phase, non-overlapping clock system with minimized skew (7.5 ns total) ensures precise timing across all components, aided by automated timing verification.
• Memory and Cache: The C Box features a 64KB write-through data cache and a 1KB translation buffer. A delayed-write algorithm and write buffer on the NMI interface optimize memory access and maintain data coherency in multiprocessor systems. The memory system provides high read (71MB/s) and write (59MB/s) bandwidths, supporting up to 128MB of memory with features like 2D interleaving, ECC, and battery backup.
• VAXBI Bus: A new 32-bit synchronous I/O bus, the VAXBI, with a 200ns cycle time, connects up to 16 devices via NBI adapters, acting asynchronously to the CPU clock and supporting high-performance DMA transfers. The bus design emphasizes random configurability and reliability.
• Reliability and Grounding: A strong focus on reliability led to features like environmental/power monitors, hardware/firmware compatibility checks, ESD protection, and ECC on memory. A logical grounding scheme addresses noise, using four distinct networks (power, logic, safety, RF/chassis) and careful interconnection strategies.
• Design Methodology & CAD: The project adopted an innovative CAD methodology, emphasizing top-down design, extensive simulation and timing verification before hardware fabrication, and a dedicated CAD team. This approach minimized design flaws and accelerated manufacturing.
• VMS Multiprocessing: VMS was enhanced to support the VAX 8800's dual processors in an asymmetric master-slave relationship, with one CPU handling all I/O. Interprocessor interrupts, cache coherency mechanisms, and interlocked instructions are utilized for synchronization and efficient task scheduling.
• Application Parallelization: The circuit simulator SPICE was successfully converted to a parallel version, CAYENNE, using VAX instructions and VMS services. This achieved a 1.7x speedup on a dual-processor VAX 8800, demonstrating the platform's advantages for compute-intensive applications.
• On-line Manufacturing Data Access (MDA): An online system was implemented to manage manufacturing data, transforming CAD outputs into standardized VMS files (DATA and DRAWING). This paperless approach streamlined product start-up and revision control, providing on-demand access to critical manufacturing information.

The VAX 8800 family represents a significant step in high-performance computing, achieved through a cohesive integration of advanced hardware design, robust software enhancements, and a forward-thinking CAD development process.