MSCP Patent 4449182

This patent describes an interface mechanism (10) designed for efficient and synchronized communication between a host processor (70) and a peripheral-controlling processor (31), particularly in data processing systems where the interconnecting I/O bus (60) lacks hardware interlock capability.

The invention utilizes a dedicated communications region (80A) in the host memory (80). Within this region, interprocessor commands and responses are exchanged as packets through ring-type queues (80D, 80E), which function as circular buffers. A command ring (80E) is used by the host to send commands to the controller, and a response ring (80D) is used by the controller to send responses back to the host.

A crucial aspect of the system is the use of an "ownership" bit or byte (278) associated with each entry in the ring queues. This bit controls access, ensuring that an entry can only be written by the designated processor when it's "empty" (owned by the other), and read by the designated processor only when it's "full" (owned by the writer). This mechanism prevents race conditions and ensures proper sequential processing without needing a hardware interlock on the bus.

A key advantage is the minimization of host processor interrupts. Interrupts are generated only for significant state transitions of the rings (e.g., when an empty ring becomes not-empty, or a full ring becomes not-full), rather than for every message. This allows both processors to operate at their own speeds asynchronously, significantly enhancing input/output and processor efficiency by reducing interrupt load on the host CPU. The system also includes mechanisms for credit-based flow control and host verification of controller integrity during initialization.