PDP-11/05 Computer Manual

This document is the official computer manual for the Digital Equipment Corporation (DEC) PDP-11/05 and PDP-11/10 computers, published in 1972 and 1973. It clarifies that the PDP-11/05 is intended for the Original Equipment Manufacturer (OEM) market and the PDP-11/10 for the end-user market, noting they are electrically identical. The PDP-11/05 offers memory configurations up to 16K words of core memory, while the PDP-11/10 is limited to 8K words.

The manual is structured into four main parts, complemented by several appendices:

1. Computer Description (Part 1):

   • Computer Components: Introduces the physical hardware, including the KD11-B processor (composed of M7260 Data Paths and M7261 Control Logic modules), core memory systems (MM11-K/L, ME11-L add-on options), backplane configurations, power supply, and essential interfaces like the Serial Communications Line (SCL) and Line Time Clock (LTC).
   • UNIBUS: Details the fundamental architecture of the DEC Unibus, a high-speed, single, common communication path connecting the processor, memory, and all peripheral devices. It explains concepts such as bidirectional lines, master-slave relationships, interlocked communication, peripheral device organization and control (where registers are addressed like memory locations), and Unibus control arbitration (Bus Requests and Non-Processor Requests with priority levels).
   • Unpacking and Installation: Provides practical guidance for setting up the computer, covering unpacking, mechanical description, mounting the unit, connecting I/O cables, and power supply connections (including voltage options and quality of AC power source).
   • Operation: Describes how to operate the PDP-11/05/10 from the console, detailing the functions of the key-lock power switch, various function switches (LOAD ADDRess, EXAM, CONTINUE, ENABLE/HALT, START, DEPosit), and console indicators. It also outlines procedures for unconditional initialization, loading programs from paper tape (using Bootstrap and Absolute Loaders), and memory dumps.

2. KD11-B Processor (Part 2):

   • General Description: Defines the KD11-B as program-compatible with earlier PDP-11 models and describes its division into Unibus control and an instruction interpreter (comprising a Data Path, Data Path Control, and Control Store).
   • Instruction Set: Presents the PDP-11 instruction set, including addressing modes, instruction timing, and a comprehensive listing of single-operand, double-operand, program control, and operate group instructions. It also highlights specific differences in the instruction set and trap sequences compared to other PDP-11 models.
   • Console Description: Delves into the detailed logic of the console's address/data register, multiplexer, clock, counter, display buffer and drivers (LEDs), and control switch mechanisms.
   • Detailed Description: Provides in-depth technical descriptions of the Data Path (including the ALU, Scratch Pad registers, Processor Status Word, and Serial Communications Line), Data Path Control, Unibus Control (DATI, DATO, DATIP, DATOB operations, bus errors, internal Unibus addresses, bus requests), and power fail/auto restart circuitry.
   • Microprogram Control: Explains the microprogrammed control approach used in the KD11-B, detailing the structure of the Control Store, microprogram branching, and the flow of instruction interpretation, interrupts, traps, and console functions.

3. MM11-K, MM11-L Memories (Part 3):

   • General Description: Covers the physical and functional aspects of the MM11-K (4K words) and MM11-L (8K words) core memory systems, including their specifications (cycle time, access time, power requirements) and key functional units (control circuits, inhibit drivers, sense amplifiers, data register, current generators).
   • Detailed Description: Provides an in-depth explanation of core array organization (3D, 3-wire ferrite cores), device and word selection logic, read/write current generation and sensing, stack discharge circuit, DC LO protection, and the detailed operation of various memory cycles (DATI, DATIP, DATO, DATOB).

4. Power Supply (Part 4):

   • General Description: Outlines the power supply unit's role in converting AC line voltage to regulated DC voltages (+15V, +5V, -15V) for the computer's components.
   • Detailed Description: Explains the AC input circuit, DC regulator module operation, and the generation of critical signals like BUS AC LO L, BUS DC LO L (for power fail detection), and LTC L (line time clock).

Overall Maintenance and Appendices: Throughout the manual, maintenance procedures are provided for all major computer subsystems (processor, memory, power supply), including diagnostic programs, adjustments, and troubleshooting charts with associated waveforms. The appendices offer technical specifications for integrated circuits (e.g., ALU, UART), detailed instruction register decode logic, comprehensive lists of computer connectors and their pin assignments (for SCL, console, Unibus), and descriptions of Unibus interface circuits and hardware characteristics.