SHAC Engineering Spec Ver 4.0 198909

This document is an engineering specification for SHAC (Single Host Adapter Chip), a VLSI chip that functions as a Single Host Adapter on a DSSI (Digital Small System Interconnect) bus.

Key aspects of SHAC and the document's content:

1. Purpose: SHAC serves as an SCA (Systems Communications Architecture) port, allowing a host system (like a VAX) to connect to and communicate with other devices, such as Mass Storage Device Controllers (MSDCs) or other VAXs, over a high-speed DSSI bus. It handles the interfacing and protocol conversion between the host's 32-bit bus and the 1-byte wide DSSI bus, implementing the CI-DSSI protocol.
2. Functionality: It performs direct host memory access (DMA) transfers at rates up to 16 MB/s on the host bus and 4-5 MB/s on the DSSI bus. SHAC incorporates an on-chip RISC processor that can load code and data from host memory, allowing for flexible configuration, adaptable behavior, and field upgrades.
3. Document Scope: The specification details the chip's external interfaces (pinout), host-addressable device registers (including CI Port registers and SHAC-specific registers), and describes the communication protocols and operations between the host and SHAC. This includes:
   • Host Bus Operation: Describes DMA read/write cycles (longword and octaword), CPU cycles (SHAC as slave), bus arbitration, and synchronous/asynchronous operating modes.
   • DSSI Bus Operation: Explains the bus phases (Bus-Free, Arbitration, Selection, Command-Out, Data-Out, Status-In), data exchange formats, and DSSI retry mechanisms.
   • Initialization & Communication: Covers chip initialization sequences (Chip Reset, MIN-Bit Reset, Common Initialization) and various aspects of host-SHAC communication, including supported/unsupported opcodes and handling of power failures.
   • Memory & Testing: Details the SHAC Shared Host Memory, its testing features (including tristate and continuity transistor features, and host access for debug), and error codes reported by SHAC.

The document is intended as a guide for those who need to interface drivers or devices that interact with the SHAC.