4449182 Interface between a pair of processors

This patent describes an interface mechanism for reliable and efficient communication between two processors in a data processing system: a host processor (70) and a peripheral-controlling processor (31), such as one found in an intelligent controller (30) for mass storage devices (40).

The core innovation addresses the challenge of inter-processor communication over an I/O bus (60) that lacks hardware interlock capabilities, common in prior art. The invention allows both processors to operate independently at their own speeds, prevents race conditions, and reduces the need for frequent processor interruptions.

The mechanism relies on a dedicated communications region (80A) located in the host's main memory (80). This region contains a pair of ring-type queues (80D for commands, 80E for responses).

1. Packet-based Communication: Commands and responses are communicated as packets. Each entry in a ring queue is a descriptor that points to another location in the communications region where the actual packet data resides.
2. Ownership Bit Synchronization: A crucial "ownership" byte or bit (278) is associated with each ring entry.
   • When a processor (source) fills an entry with a command or response, it sets the ownership bit to a first state.
   • The other processor (recipient) can only read that entry when the ownership bit is in this specific state.
   • Once the recipient reads and processes the entry, it changes the ownership bit to a second state, signaling that the entry is now empty and available for reuse by the source.
3. Flow Control: Each processor keeps track of the rings' status to prevent sending more messages than the rings can hold, ensuring efficient data exchange without overwhelming either side.

This system effectively buffers asynchronous command and response packets, eliminating the need for complex hardware interlocks on the I/O bus and enabling the processors to operate with substantial independence and reduced interrupt overhead.