RP03 ISS 715 Schematic

This document provides a comprehensive technical overview and detailed schematic diagrams for the electronic gate, a core component of the system.

The document begins by identifying the Printed Wiring Assemblies (PWAs) located within the electronic gate, listing each PWA's gate position, part number, and functional title (e.g., Read/Write Paddle, Defect Detector, Power Control, various Registers and Selectors). A corresponding diagram visually presents the physical placement of these PWAs and the system's power supply voltage levels, including nominal values and permissible ranges.

It then serves as a technical guide for interpreting the included logic and schematic diagrams, outlining:

• Standard logic voltage levels: Defined as 'down/low' (0.0 to +0.5V) and 'up/high' (+2.5 to +5.0V), with specific voltage ranges provided for various power supplies (-48V, -12V, +5V, +12V, +20V, +30V). Voltages outside these ranges are considered spurious.
• Signal line naming conventions: Explaining how signal lines are named, including their source, destination, socket, pin numbers, and logic state indicators (e.g., "0X+3").
• Pin connections: Detailing how input/output pins are shown, corresponding to electronic gate sockets or other components.
• Waveform indications: Noting symbols used to indicate associated waveforms, particularly for seek operations.

The bulk of the document comprises detailed logic and schematic diagrams for numerous Printed Wiring Assemblies (PWAs) and functional blocks, illustrating the intricate circuitry for components like Read/Write Paddles, Selectors (e.g., Select 0-9, Select 10-19), various Registers (Head Address, Cylinder Address), Detectors (Defect, Cylinder), Control units (Power, Access), and Power Drivers. While most PWA schematics are provided, some proprietary circuit diagrams are noted as exceptions.