21264/EV68CB and 21264/EV68DC Hardware Reference Manual

This document, the "21264/EV68CB and 21264/EV68DC Hardware Reference Manual," serves as a comprehensive technical reference for system designers and programmers utilizing these Alpha microprocessors (referred to as EV68CB/EV68DC).

The manual begins with an introduction to the Alpha architecture and a high-level overview of the EV68CB/EV68DC's key features, including its superscalar, pipelined design, on-chip memory management unit (MMU), floating-point units, and various caches.

A significant portion of the document delves into the internal architecture, detailing the Instruction Fetch, Issue, and Retire Unit (Ibox), Integer Execution Unit (Ebox), Floating-Point Execution Unit (Fbox), On-chip Caches (Icache, Dcache), Memory Reference Unit (Mbox), and External Cache and System Interface Unit (Cbox). It explains pipeline organization, instruction issue and retire rules, memory and I/O address space handling, and performance measurement support.

Further chapters cover:

• Hardware Interface: The physical aspects of the microprocessor, including its logic symbol, signal names, pad assignments, and mechanical specifications.
• Cache and External Interfaces: The intricate details of how the processor interacts with external components, specifically the second-level cache (Bcache) and the system bus, encompassing cache coherency protocols, data movement, and clocking mechanisms.
• Internal Processor Registers: A comprehensive listing and description of the various internal processor registers (IPRs) used for configuring and monitoring chip functions.
• Privileged Architecture Library (PALcode): Explanation of PALcode's role in handling operating system primitives like context switching, interrupts, exceptions, and memory management, along with its specific instructions and operational guidelines.
• Initialization and Configuration: Detailed sequences for power-up, fault, warm, and sleep mode resets, and the initialization of internal arrays and external interfaces.
• Error Detection and Handling: Mechanisms for identifying and managing hardware errors, such as ECC (Error Correction Code) and parity checks in caches and data buses.
• Electrical Data & Thermal Management: Electrical characteristics (DC/AC ratings, power supply) and thermal considerations (operating temperatures, heat sink specifications) to ensure proper system design and operation.
• Testability and Diagnostics: Features supporting chip and system-level testing, including the IEEE 1149.1 Test Access Port and SROM-based initialization.

Appendices provide summaries of the Alpha instruction set, BSDL descriptions for the boundary-scan register, and specific guidelines for PALcode implementation and Bcache interface details.