Alpha 21264/EV67 Microprocessor Hardware Reference Manual

This document is the Alpha 21264/EV67 Microprocessor Hardware Reference Manual, published by Compaq Computer Corporation in March 2002. It serves as a comprehensive guide for system designers and programmers using the Alpha 21264/EV67, a high-performance, superscalar, and pipelined RISC processor that implements the 64-bit Alpha architecture.

The manual provides detailed information across several key areas:

1. Introduction and Features: Introduces the Alpha architecture and highlights the 21264/EV67's specific capabilities, such as its ability to issue up to four instructions per CPU clock cycle, its on-chip memory management unit with dual 128-entry Translation Buffers (ITB and DTB), two pipelined floating-point units, and support for various data types and virtual/physical addressing.
2. Internal Architecture: Describes the major functional hardware units including the Instruction Fetch, Issue, and Retire Unit (Ibox), Integer Execution Unit (Ebox), Floating-Point Execution Unit (Fbox), on-chip Instruction (Icache) and Data (Dcache) caches, Memory Reference Unit (Mbox), and External Cache and System Interface Unit (Cbox). It details the 7-stage pipeline organization, instruction issue and retire rules, memory and I/O address space handling, replay traps, and performance measurement support.
3. Hardware Interface: Provides mechanical specifications, logic symbols, signal names, functions, and pin assignments for the 587-pin PGA package, crucial for system integration.
4. Cache and External Interfaces: Explains the interactions with the external second-level (Bcache) cache and the system interface, including cache coherency protocols, lock mechanisms, bus commands, clocking, and data movement.
5. Internal Processor Registers: Lists and describes the extensive set of internal processor registers (IPRs) within the Ebox, Ibox, Mbox, and Cbox, which control and monitor the processor's functions.
6. Privileged Architecture Library (PALcode): Details the specialized macrocode used for operating system primitives, context switching, interrupts, exceptions, and memory management, including reserved opcodes and IPR access mechanisms.
7. Initialization and Configuration: Outlines the power-up, fault reset, warm reset, and sleep mode flows, as well as array initialization and external interface setup.
8. Error Detection and Error Handling: Covers mechanisms like Error Correction Code (ECC) for data buses and parity checking for caches, describing how various errors are detected and managed.
9. Electrical Data and Thermal Management: Provides electrical characteristics (DC/AC specifications) and guidelines for thermal design, including operating temperatures and heat sink specifications.
10. Testability and Diagnostics: Describes built-in self-test (BiST) features, serial ROM loading, and IEEE 1149.1 (JTAG) port functionality.

The manual is a comprehensive technical reference for anyone designing hardware or developing low-level software for systems based on the Compaq Alpha 21264/EV67 microprocessor.