Alpha 21264/EV6 Microprocessor Hardware Reference Manual

This document is the Alpha 21264/EV6 Microprocessor Hardware Reference Manual, providing a comprehensive technical guide for system designers and programmers using this microprocessor. Published by Compaq Computer Corporation in March 2002, it details the Alpha 21264/EV6, a superscalar, pipelined, 64-bit Reduced Instruction Set Computing (RISC) processor.

Key aspects covered in the manual include:

1. Architecture Overview: Introduces the Alpha architecture, emphasizing its 64-bit load/store RISC design, multiple instruction issue, and support for various integer (8-, 16-, 32-, 64-bit) and floating-point (IEEE 32/64-bit, VAX 32/64-bit) data types.
2. Microprocessor Features: Highlights the 21264/EV6's ability to issue up to four instructions per CPU clock cycle, its peak instruction execution rate, and advanced features like an on-chip, demand-paged Memory Management Unit (MMU) with separate 128-entry Instruction and Data Translation Buffers (ITB/DTB). It supports programmable 48-bit or 43-bit virtual addresses and a 44-bit physical address space.
3. Internal Architecture: Describes the major functional units:
   • Instruction Fetch, Issue, and Retire Unit (Ibox): Manages instruction flow, branch prediction, register renaming, and issue queues (Integer and Floating-Point).
   • Integer Execution Unit (Ebox) and Floating-Point Execution Unit (Fbox): Handle instruction execution.
   • On-chip Caches: Includes a 64KB virtually-addressed Instruction Cache (Icache) and a 64KB virtually-indexed, physically-tagged Data Cache (Dcache).
   • Memory Reference Unit (Mbox): Controls the Dcache and manages memory operations through Load Queue (LQ), Store Queue (SQ), and Miss Address File (MAF).
   • External Cache and System Interface Unit (Cbox): Controls interaction with external caches (Bcache) and the system bus, including a duplicate Dcache tag array for coherency.
4. Pipeline Organization: Details the 7-stage pipeline, instruction issue rules, latencies, and instruction retirement logic.
5. Cache and External Interfaces: Explains the external bus functions, transactions, and clocking mechanisms for the second-level (Bcache) and system interfaces. It covers cache coherency protocols (MESI), a lock mechanism for atomic operations (LDxL/STxC), and data movement protocols.
6. Internal Processor Registers (IPRs): Lists and describes various control and status registers within the Ebox, Ibox, Mbox, and Cbox, which are essential for configuring and monitoring the processor.
7. Privileged Architecture Library Code (PALcode): Explains the specialized software routines that provide operating system primitives (e.g., context switching, interrupts, memory management) and offer privileged access to hardware functions.
8. Initialization and Configuration: Describes the power-up reset sequence, fault reset, sleep mode, array initialization, and external interface setup.
9. Error Detection and Error Handling: Outlines the processor's mechanisms for detecting and handling errors, including ECC (Error Correction Code) for data buses and parity checking for internal caches, along with responses to various error conditions.
10. Electrical and Thermal Data: Provides specifications for electrical characteristics (DC/AC), power supply sequencing, and thermal management, including operating temperatures and heat sink requirements.
11. Testability and Diagnostics: Details test pins, SROM/serial diagnostic port, and IEEE 1149.1 (JTAG) boundary-scan features for testing and debugging.

The manual serves as a critical resource for anyone involved in designing systems or writing low-level software for Compaq's Alpha 21264/EV6 microprocessor-based platforms.