Tsunami/Typhoon 21272 Chipset

This "Tsunami/Typhoon 21272 Chipset Hardware Reference Manual" is a comprehensive technical document published by Compaq Computer Corporation in October 1999. It serves as a support and reference guide for engineers designing dual-processor and uniprocessor systems using the 21264 Alpha microprocessor and the 21272 core logic chipset.

The manual provides detailed information on the architecture, internal design, external interfaces, and specifications of the 21272 chipset, which consists of three primary application-specific integrated circuits (ASICs):

1. Cchip (Controller chip): Controls other chipset components and interfaces with the CPU's command and address buses. It manages DRAM memory arrays and the TIGbus (for interrupts and flash ROM). Variants include the 21272-C1 (supporting up to two CPUs) and the 21274-C1 (Typhoon variant, supporting up to four CPUs).
2. Dchip (Data Slice chip): Interfaces with the system data bus, facilitating data transfer between the CPU, DRAM memory, and Pchips. Systems can be configured with two, four, or eight Dchips (21272-D1, or 21274-D1 for heavier memory loads).
3. Pchip (Peripheral Interface chip): Serves as the interface between the PCI bus and the rest of the system, communicating with the Cchip and Dchips via the CAPbus and PADbus. Systems can incorporate one or two Pchips.

Key features and capabilities of the 21272 chipset highlighted in the document include:

• Support for the 21264 Alpha CPUs.
• Ability to interface with up to two 64-bit, 33-MHz PCI buses.
• Support for a large main memory capacity (16MB to 4GB using 16Mb/64Mb SDRAMs, with Typhoon supporting up to 8GB), featuring low-latency access and ECC (Error-Correcting Code).
• Achieves a very high peak memory bandwidth of 2.67 GB/s per processor.
• Flexible system configurations allow for varying numbers of Dchips, Pchips, and memory bus widths.

The manual covers a wide range of technical details, including:

• Pinouts: Comprehensive lists and descriptions of signal interface pins for each ASIC.
• Electrical and Mechanical Specifications: Details on absolute limits, power requirements, DC and AC characteristics, and package dimensions.
• Chip Architecture: In-depth descriptions of the internal structures, queues, and operational mechanisms of the Cchip, Dchip, and Pchip.
• System Memory: Explanation of memory organization, addressing schemes (including split/nonsplit arrays and address XORing for Typhoon), and control signals.
• Programmer's Reference: Information for software developers on system address mapping, address translation (PIO, DMA, scatter-gather), and the various internal chipset registers (CSRs).
• Clock Generation and Management: Details on chipset clocking, PCI bus clocking, SDRAM clocking, and CPU interface clock forwarding.
• Reset, Initialization, and Power Management: Sequences for hardware and firmware initialization (including SDRAM) and support for ACPI C3 (sleep) states.
• Error Handling: Mechanisms for detecting and reporting memory data errors and PCI bus errors.

This document is essential for system designers, software developers, and hardware engineers involved in the development and implementation of systems based on the Tsunami/Typhoon 21272 chipset.