H-551 551dectapeCtlr

This document is a technical manual for the DECtape system, primarily focusing on the DECtape Control Type 551.

The manual is structured into several chapters:

• Chapter 1: Introduction and Description outlines the purpose of the DECtape Control Type 551 in transferring binary data between DECtape Transports (Type 555) and the PDP-6 Arithmetic Processor. It describes the system's functional features, such as fixed-position data storage, 10-track read/write heads with redundant and Manchester phase recording, and bidirectional operation. Physical specifications, electrical requirements, and a list of pertinent supporting documents are also included.

• Chapter 2: System Description details the overall DECtape system architecture, comprising the PDP-6 processor, Data Control Type 136, DECtape Control Type 551, and Type 555 Dual DECtape Transports. It describes the 5-channel recording format, emphasizing the roles of timing and mark tracks for synchronization and data organization. The fixed-length block format, interblock zones, and various mark codes (e.g., Block Mark, Data Sync, End Marks) are explained, highlighting their symmetrical design for reading/writing in both directions. The chapter also provides an overview of the key internal hardware registers within the Type 551 control, such as control, status, data buffers, mark track window, and timing registers.

• Chapter 3: Theory of Operation delves into the detailed operational procedures. It explains the system's initialization sequence, I/O bus interface, command decoding, and common functions like timing and mark track processing. Detailed sections cover the mechanics of writing (block marks, data, and "write all" operations, including checksum computation and interblock zone handling) and reading data, highlighting the differences in data flow. The document also provides comprehensive explanations of automatic error checking (mark track errors, active state errors, illegal operations, incomplete blocks) and program interrupt mechanisms. Finally, it offers in-depth discussions of specific critical circuit modules: the Manchester Reader and Writer Type 4523, Mark Track Decoder Type 4260, and Level Standardizer Type 1501.

• Chapter 4: Interface lists the various standard and nonstandard logic interface signals exchanged between the DECtape control and other components (I/O Bus, Type 555 Tape Transports, and Data Control 136) in tabular format.

• Chapter 5: Programming is noted as "To be supplied" in the provided document, indicating no content is available for this section.

• Chapter 6: Maintenance provides extensive guidelines for both preventive and corrective maintenance. Preventive maintenance includes mechanical checks, power supply verification, and adjustments for various internal modules. Marginal checks are detailed for identifying components at the edge of their operating limits. Corrective maintenance outlines a systematic approach to diagnosing faults, from preliminary investigation and system-level troubleshooting to circuit-level analysis, repair procedures, and validation testing. A comprehensive list of recommended spare parts (modules, semiconductors, pulse transformers, etc.) is also provided.

• Appendix 1: Engineering Drawings serves as a guide to the accompanying engineering drawings, explaining the drawing number conventions, coordinate systems, module identification, and the various circuit and logic signal symbols used in the schematics.