A Memory Subsystem for the i486™ CPU including Second Level Cache

This document details the design of a high-performance memory subsystem for the Intel i486™ CPU, emphasizing features that optimize memory access and overall system performance.

Key aspects of the design include:

1. Second-Level Cache: The subsystem incorporates an optional 485Turbocache module, a 128KB (cascadable to 512KB), two-way set-associative, write-through, look-aside cache. This cache significantly reduces read cycle latency by providing 16-byte cache lines to the i486 CPU with zero wait states, greatly improving performance for multitasking and multiuser operating systems.
2. DRAM Interface Optimization:
   • Interleaving: Alternate 32-bit DRAM banks are accessed based on the address to support the i486's burst bus feature, allowing single-clock DWORD accesses during cache line fills.
   • Write Posting: This technique reduces write cycle latency by overlapping bus cycles, achieving an average write latency of 2.5 clocks. Write data and addresses are held in registers after the CPU's ready signal, allowing the CPU to proceed with subsequent operations while the write to DRAM completes.
3. Burst Cycles: The design fully supports the i486's burst bus cycles for efficient transfer of cache lines, code fetches, and data loads.
4. Control Logic: The memory control logic is implemented using a distributed state machine architecture across multiple Programmable Logic Devices (PLDs). This modular design manages various signals, including cycle tracking, address path control (with a burst address generator), data path control, RAS#/CAS# timing, and write control.
5. Performance Metrics: The subsystem achieves zero-wait-state read accesses from the second-level cache. For main memory, page hits are typically completed in 3 clock cycles for the first access and 1 for subsequent burst accesses, while page misses take 7 clocks for the first access and 1 for subsequent. Write cycles average 2.5 clocks. The document also details critical DRAM timing restrictions necessary for 33 MHz operation.

The document provides extensive timing diagrams, state machine definitions, and signal descriptions to guide hardware designers in implementing and optimizing i486-based memory systems.