decnetRSX internalsCourse 1983

Order Number: XX-787BF-66

This document, "DECnet - RSX internals," provides a comprehensive overview of the architecture, evolution, components, and operational aspects of DECnet as implemented on RSX operating systems by Digital Equipment Corporation.

The document traces the evolution of DECnet/RSX through various phases (Phase I to V, spanning 1975 to 1982+), detailing the supported operating systems in each phase, including various RSX versions, IAS, RSTS/E, RT-11, VAX/VMS, TOPS-20, ULTRIX, and MS-DOS.

A central element is the Communications Executive (CEX), which offers core functionalities:

  • Simple Scheduler: Manages process execution with no pre-emption and minimal context setup, driven by a FIFO queue.
  • Timer Support: Provides both 1-second and 100-millisecond granularity timers for various network operations.
  • Interrupt Service Routines: Handles fast interrupt services and allows co-routines to manage processor priority.
  • Buffer Management: Routines for allocating and deallocating Communication Control Blocks (CCBs), Small Data Buffers (SDBs), and Large Data Buffers/Receive Data Buffers (LDBs/RDBs), including dynamic allocation and recovery.
  • Common Subroutines: Standard utilities for queue manipulation, buffer moves, and event logging. CEX integrates closely with the RSX executive, allowing network operations to leverage existing system services. A minimal configuration consists of the Communications Executive, an Auxiliary Process (AUX), and a Network Pool. The AUX process handles scheduler and timer entries, modem control, and powerfail recovery.

The document then details the process layers that form the network communication stack:

  • LLC (Logical Link Control): Channel-oriented, managing virtual circuits.
  • DLC (Data Link Control): Point-to-point or multipoint, providing error-free paths to adjacent nodes.
  • DDM (Device Driver Modules): Device controller/line-oriented, providing device-specific control. These layers interact through a mix of direct subroutine calls and queued requests. Each process layer maintains specific databases for controlled entities (e.g., channels, lines, controllers), which are created during the network loading process.

The NSP/NETACP Implementation section covers the user interface functions available for network tasks (e.g., declaring tasks, requesting/accepting connections, transmitting/receiving messages) and the underlying device driver data structures. It illustrates the initiation, reception, and transmission of I/O packets, along with the formats of various NSP messages (Data, Acknowledgement, Control) and how they are segmented and reassembled. Detailed flowcharts describe the processes of Logical Link Creation, Operation (receive and transmit), and Disconnection.

Transport and Routing are discussed in depth, outlining features like packet forwarding, adapting to network topology changes, routing database updates, and congestion control. Key components like the XPT (Transport Network process) and RCP (Routing Control task) are introduced, along with Phase IV+ improvements in area routing. The document also includes a comparison of routers and bridges, and explains path splitting concepts.

The process of Loading the Network Software is described, outlining the roles of key files (CEX.TSK, CETAB.MAC, CETAB.TSK, process task images, and template files) and utilities (NCP, NM, NMVACP, NTINIT, and NTL). It details the steps involved in initializing network components and data structures.

Finally, the document provides Debugging Aids and Helpful Hints, introducing various utilities such as UNSGEN (Unsupported utility Generation), CEDUMP (Comm/Exec Dump), TRC (Transport trace utility), and TRXCTL/TRXCOL (CTERM trace utility). Examples of their output are provided to assist with system monitoring and troubleshooting. It also includes parameters for tuning DECnet-RSX for satellite links.

Throughout the document, extensive MACRO definitions and detailed layouts of internal data structures (e.g., for Communication Control Blocks, Process Descriptor Vectors, Logical Link Tables, and various flags) are provided, offering a deep insight into the low-level mechanics of DECnet-RSX.

XX-787BF-66
2000
112 pages
Quality

Original
2.3MB

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