Alpha System Reference Manual

This document is a comprehensive technical reference for the Alpha System Architecture, Version 7, published by Digital Equipment Corporation. It is organized into three main parts and several appendices, detailing the architecture's common features, specific implementations for various operating systems, and console interfaces.

Part One: Common Architecture outlines the core 64-bit load/store RISC design of the Alpha system. It describes the instruction set, covering various formats (memory, branch, operate, floating-point, PALcode) and detailed descriptions of integer arithmetic, logical, shift, byte manipulation, and floating-point operations. This section also specifies the system's registers (integer, floating-point, lock, processor cycle counter) and critical architectural implications for high-performance system programming, including data sharing mechanisms (atomic operations, load-locked/store-conditional), memory coherency, read/write ordering, and arithmetic trap handling. It introduces PALcode as a flexible, OS-agnostic software library designed to implement complex, privileged, and low-level hardware functions consistently across different Alpha implementations.

Part Two: Specific Operating System PALcode Architecture delves into the unique architectural specifics and PALcode instruction sets for three major operating systems supported by Alpha: OpenVMS Alpha, DIGITAL UNIX, and Windows NT Alpha. For each OS, it details register usage (e.g., Processor Status, Stack Pointers, Internal Processor Registers), memory management (virtual address spaces, page tables, translation buffers, address space numbers, memory faults), process structures (context blocks, Asynchronous System Traps), and the mechanisms for handling exceptions, interrupts, and machine checks via PALcode routines.

Part Three: Console Interface Architecture describes the console subsystem's fundamental role in initializing, bootstrapping, and controlling Alpha systems. It covers console implementations (embedded, detached), the Hardware Restart Parameter Block (HWRPB) and its numerous fields, environment variables, and a comprehensive set of Console Callback Routines. These routines facilitate interactions for terminal I/O, generic device access, and system management during system startup, restarts, and error halts. It also details different bootstrap loading methods (disk, tape, ROM, network) and the critical BB_WATCH timekeeping mechanism.

Finally, the Appendices provide supplementary technical information, including software considerations for optimizing code performance, detailed IEEE floating-point conformance, comprehensive instruction summaries (opcodes, function codes), registered system and processor identifiers, and documentation of architectural waivers and implementation-dependent functionalities. The document emphasizes that distribution is restricted due to its confidential nature.