This document is the Version 5 reference manual for the Digital Alpha 64-bit load/store RISC architecture, intended for Digital's restricted distribution. It comprehensively details the Alpha architecture, emphasizing high performance through features like multiple instruction issue and multiprocessing.
The manual is organized into three main parts and several appendices:
- Part One: Common Architecture outlines the core architecture, covering data formats, instruction sets (integer, floating-point, control, logical, shift, and byte manipulation), system architecture (memory behavior, caching, data sharing, read/write ordering, and arithmetic traps), common PALcode (Privileged Architecture Library) architecture, console subsystem, and input/output.
- Part Two: Specific Operating System PALcode Architecture describes how OpenVMS Alpha and DEC OSF/1 operating systems interact with the Alpha architecture, including their unique PALcode instructions, memory management, process structures, exceptions, interrupts, and internal processor registers.
- Part Three: Platforms details the architected platform implementation, focusing on the console subsystem overview, its interface with operating system software, and various system bootstrapping processes (cold, warm, multiprocessor, and network).
Appendices provide further details on software considerations, IEEE floating-point conformance, instruction encodings, registered system and processor identifiers, and console implementation functions. The document highlights Alpha's design principles, such as maintaining binary compatibility, avoiding operating system bias, and providing hints for higher-speed implementations.