System Introduction

This document provides a technical introduction and architectural overview of the Digital Equipment Corporation (DEC) PDP-8/E and PDP-8/M computer systems.

Key sections include:

• PDP-8/E Processor: Described as a fast, general-purpose, 12-bit, parallel-transfer computer using 2's complement arithmetic. It features a 4096-word random-access magnetic core memory with a 1.2/1.4 microsecond cycle time. The system is self-contained and modular, allowing for various peripheral expansions.
• PDP-8/M OEM Processor: A functionally identical version of the PDP-8/E designed for original equipment manufacturers. It is built around a single OMNIBUS architecture (expandable to three) and offers specific operator or programmer panel configurations.
• Computer Organization: The system architecture relies on the "OMNIBUS" to connect the central processor, core memory, and input/output facilities.

• Major Components: The document details the internal modules of the system, including:

  • Major Registers: The Accumulator (AC), Multiplier Quotient (MQ), Program Counter (PC), Central Processor Memory Address (CPMA), and Memory Buffer (MB).
  • Control Modules: Register Controls, Bus Loads for maintaining signal integrity, and the Timing Generator for synchronized operations.
  • Memory System: Describes the 4K core memory modules, including the XY Driver, Memory Stack, and Sense/Inhibit modules.
  • Processor States: Outlines the execution cycle of the computer through three primary states: FETCH, DEFER, and EXECUTE.

• Interfaces: Details are provided for the Programmer’s Console and the Teletype (ASR 33) interface for data entry and system operation.