Pdp-8 Instruction Test Part 2b

Summary

This document is a technical specification and program listing for the "PDP-8 Instruction Test Part 2b." Created in 1968 by the Diagnostic Group, this program is designed to verify the functionality of the PDP-8 processor’s 2s complement addition (TAD) and rotate logic (RAL, RTL, RAR, RTR).

Key features of the program include:

• Testing Logic: The test utilizes pseudo-random numbers to verify the 2s complement adder and performs over 8,000 pattern tests on rotate instructions to ensure correct register and link bit manipulation.
• Operator Control: Execution is governed by the PDP-8's SWITCH REGISTER, allowing users to toggle specific functionalities such as "scope mode" (which loops on errors for troubleshooting), error halting, and test selection.
• Error Reporting: If the hardware fails a test, the program can print out detailed information, including the original pattern, the incorrect result, the expected result, and the specific operation that triggered the failure.
• Execution: The program includes the complete assembly code listing for deployment on the PDP-8, including memory locations, subroutines for printing and logic comparison, and the specific entry points for the addition and rotation test portions.

This diagnostic tool is intended to be run following a successful execution of "Instruction Test 2A" to ensure the reliability of the system's core arithmetic and logic modules.