Logical Functions

This document provides a detailed technical explanation of the operations, architecture, and logical functions of the PDP-8 computer. The text is divided into three primary chapters (2, 3, and 4) covering the following key areas:

• Logical Functions and Operations (Chapter 2): Covers the sequences of events during manual, programmed, and automatic operations. It details specific instructions (AND, TAD, ISZ, DCA, JMS, JMP, IOT, and OPR), how instructions are decoded and executed, and the procedures for data breaks and program interrupts.
• Processor Logic (Chapter 3): Explains the hardware logic of the PDP-8 processor, including the power clear generator, timing signal generator, run and pause controls, instruction register, and major state generator. It also details the Type 182 Extended Arithmetic Element (EAE) for higher-speed operations and the Type 681 Data Line Interface for Teletype communication.
• Core Memory (Chapter 4): Describes the organization and operation of the PDP-8 core memory system, including how addresses are selected, the function of sense amplifiers and inhibit drivers, and the power supply requirements. It also covers the Type 183 Memory Extension Control, Type 184 Memory Modules, and the optional Type 188 Memory Parity feature, which includes error detection logic.

The manual includes numerous references to engineering drawings, timing diagrams, and logic gates to explain how the physical circuits facilitate the computer's operational states and instruction execution.