Processor Flow Chart

This document contains technical engineering diagrams and documentation for the PDP-8/E computer system. Specifically, it provides:

• Processor Flow Chart: A logic diagram illustrating the operational states and data path transitions (Fetch, Defer, Execute) for the PDP-8/E processor.
• Timing Diagrams: Two detailed timing sheets illustrating internal memory signals, general timing pulses (TS1L through TS4L, TP1H through TP4H), and cycle durations for both fast and slow cycles, as well as external I/O cycle operations.
• Major Registers (KK8/E): Detailed circuit schematic diagrams for the system's "Major Registers" board. This includes a physical component layout (Module M8320) and a corresponding logic schematic showing the interconnection of integrated circuits (such as 74151 and 7483 series logic chips) that form the core register architecture.