Fpp Assembler

This document serves as a user's guide for the FPP Assembler, designed for the PDP-12 Floating Point Processor. The assembler translates PDP-8 and floating point mnemonic operation codes into binary machine code.

Key information provided in the guide includes:

• Hardware Requirements: A minimum configuration of a PDP-12/20 with 8K of core memory, with an FPP-12 processor strongly recommended.
• Syntax and Expressions: Covers statement formatting, tag labeling, and the three supported expression formats (integer, double precision, and floating point).
• Instruction Formats: Details the various formats for PDP-8 memory reference, IOT, and Operate instructions, as well as the specific memory reference and index register formats for the FPP.
• Pseudo-operations: Explains assembler control functions such as radix setting (OCTAL/DECIMAL), program location control (ORG, PAGE), literal management (LITORG), and conditional assembly (IFnnn).
• Operational Procedures: Instructions for loading and exiting the assembler within the DIAL-MS environment.
• Internal Description: Provides insight into the assembler’s two-pass logic, including op-code handlers, major subroutines, and key system variables.
• Appendices: Includes summaries of the character set, operators, pseudo-ops, FPP symbol definitions, error messages, and a system flow chart to aid in understanding the assembly process.