EV6 Chip Specification, Revision 2.0

This document is the second revision of the EV6 chip specification, an in-depth technical manual for Digital's third-generation Alpha RISC CPU, dated April 12, 1996. It provides a comprehensive overview of the EV6's architecture, interfaces, and operational parameters.

Key updates in this revision include a major rewrite of the external interface, substantial changes to the PAL/IPR (Privileged Architecture Library/Internal Processor Register) sections, and new electrical and packaging information. Further documentation is anticipated to detail electrical and packaging, reset/initialization, test/debug features, PLL operation, and error handling.

The specification covers the EV6's relation to the Alpha Architecture (extensions, implementation-specific features, and exception handling), its internal architecture (chip organization into units like Ebox, Fbox, Ibox, Mbox, Cbox, Icache, Dcache, pipeline stages, memory/I/O access, and prefetching), and its external interfaces (System and Bcache ports, including address spaces, cache coherence, and clocking). It also details Privileged Architecture Library (PALcode) and Internal Processor Registers (IPRs), IEEE floating-point conformance, error detection and handling, electrical characteristics, and packaging information. Additionally, the document includes an appendix outlining PAL coding restrictions. The document is marked as "Digital Confidential."