EV5 CPU Chip Internal Specification

This document details the internal specifications of the EV5 CPU Chip, a high-performance, single-chip implementation of the Alpha Architecture. The chip's design is organized around several key functional units:

1. IBOX (Instruction Box): Responsible for instruction fetching, branch prediction, and instruction issue. It includes an 8KB direct-mapped I-Cache with refill buffers, a 64-entry fully associative Instruction Translation Buffer (ITB), and a 2Kx2 bit Branch History Table (BHT). The IBOX manages a 7-stage pipeline (S-1 to S7) for processing instructions, handling PC calculation, instruction buffering, slotting to execution units, and managing traps and interrupts.
2. EBOX (Execution Box): The integer execution unit, redesigned from EV4. It handles integer arithmetic, logical, and byte manipulation instructions. The EBOX features a 40-entry register file, two 4-stage execution pipelines (E0 and E1) that are fully bypassable, and dedicated units for addition, logic operations, shifts, byte zapping, multiplication, and branch condition logic. E0 handles shifts, byte manipulation, stores, and multiplies, while E1 manages instruction flow control.
3. FBOX (Floating-point Box): Dedicated to floating-point operations. It contains two pipelined functional units: an ADD pipe and a MULTIPLY pipe, along with load and store ports for its register file. The FBOX evaluates floating-point branch outcomes and conditional moves, and its operations are closely integrated with the IBOX and EBOX for instruction issue and retirement.
4. MBOX (Memory Box): Manages loads and stores from the IBOX for the D-stream. Key functions include Data Translation Buffer (DTB) lookups for virtual-to-physical address translation, Dcache hit/miss calculations, data formatting, and queuing memory requests in the Miss Address File (MAF) for the S-Cache. It also ensures strict read/write ordering and detects D-stream faults and Dcache parity errors.
5. CBOX (Cache Box): Oversees the chip's second-level cache (SCache) and interfaces with the system's data stores. It consists of the SCache Arbiter Unit (SAU) for prioritizing access, the Write Buffer Data Unit (WBU) for storing write data and managing reissues, and the Bus Interface Unit (BIU) for external memory communication. The CBOX handles system probes, invalidates, fills, and ECC error detection/correction for the cache hierarchy.
6. Caches: The EV5 CPU employs a two-level cache system.
   • Level 1 (L1): An 8KB direct-mapped virtual I-Cache and a 16KB direct-mapped write-through physical D-Cache.
   • Level 2 (L2): A 96KB 3-way set associative write-back physical S-Cache, which is a unified instruction and data cache.

The document details the functional descriptions, instruction flows, timing, register interfaces, and error handling mechanisms for these components, outlining their roles in processing instructions and managing memory within the Alpha Architecture.