DECchip 21164-AA EV5 CPU Functional Specification Rev 1.9 199310

This document is the Functional Specification for the DECchip 21164-AA (EV5 CPU), a high-performance, single-chip microprocessor developed by Digital Equipment Corporation, implementing the Alpha architecture.

Key Features and Architecture:

• Super-scalar and Super-pipelined: Built on CMOS-5 (0.5 micron) technology, the chip is designed to issue up to four Alpha instructions per cycle, featuring a 7-stage integer pipeline and a 9-stage floating-point pipeline.

• Functional Units: It integrates five main units:

  • Ibox: Responsible for instruction fetching, decoding, issuing, PC management, and managing the on-chip 8KB instruction cache (Icache) and a 48-entry Instruction Translation Buffer (ITB). It also handles interrupts and traps.
  • Ebox: Contains two 64-bit integer execution units and calculates effective addresses for memory operations.
  • Mbox: Manages load and store operations, data stream memory management, a 64-entry Data Translation Buffer (DTB), outstanding load misses, the write buffer, and the 8KB dual-ported data cache (Dcache).
  • Cbox: Controls the external interface and cache coherence protocol. It manages the 96KB 3-way set-associative second-level cache (Scache) and supports an optional external third-level cache (Bcache).
  • Fbox: Houses two high-throughput floating-point execution units that support both DEC and IEEE floating-point data types.

• Memory and Caching: Features a demand-paged memory management unit with on-chip Translation Buffers, multi-level on-chip caches (Icache, Dcache, Scache), an on-chip write buffer, and support for external cache configurations.

• System Integration: Designed for a wide range of systems, from uni-processor workstations to multiprocessors, with a 128-bit separate data and address bus.
• Packaging: Packaged in a 503-pin IPGA.
• Testing and Debugging: Includes on-chip performance counters and various testability features for chip and module-level testing and analysis.

Purpose: The document details the external interface and programming aspects specific to the DECchip 21164-AA's implementation, rather than providing a detailed internal hardware description or a general overview of the Alpha architecture.

Important Notes: The specification explicitly states that the information is subject to change without notice and does not constitute a commitment for future products. It defines critical terms like "UNPREDICTABLE" and "UNDEFINED" to clarify expected behavior in different error or unspecified scenarios.