Dual Binary to Decimal Decoder MI63

This document is a technical schematic from Digital Equipment Corporation, dated 1969, detailing the circuit design for a "Dual Binary to Decimal Decoder" (MI63). The schematic shows the wiring for two Fairchild 9301 decoder chips, including inputs (labeled $2^0$ through $2^3$), output pins, and power supply connections (+5V and ground) with associated capacitors. It includes notes specifying that pin 8 is grounded, pin 16 is +5V, and the capacitors are .01 MFD. The document also includes administrative information such as revision status, engineering sign-offs, and a blank transistor and diode conversion chart.