Principles of Operation

This document serves as an introduction to the operation of the PDP-8/E processor. It provides a structured breakdown of the system into eight functional areas, including the OMNIBUS, Timing Generator, Memory System, Central Processor, Major Registers, Power Supply, Bus Loads, and Teletype Control.

Key topics covered include:

• System Architecture: The OMNIBUS acts as the primary data and signal pathway. The processor utilizes quad-size modules for each functional area.
• Data Paths and Timing: The document details how data moves between major registers (PC, CPMA, MB, AC, MQ) and the OMNIBUS, supported by specific timing states (TS1–TS4) and pulses (TP1–TP4) generated by the M8330 module.
• Operations: It explains the four major processor states (FETCH, DEFER, EXECUTE, and DMA) and provides flow diagrams for instructions and system start-up/stop procedures.
• Memory System: Describes the standard MM8-E core memory, including the organization of core mats, the coincident-current selection technique, and detailed read/write signal logic.
• Operator Interface: Discusses the functions of the Programmer's Console (KC8-EA) and Operator's Panel (KC8-M) for manual operations such as loading addresses, depositing/examining memory, and controlling processor states.