A Pdp-8 Floating Point Software Package Simulator Using A Fpp-12 Floating Point Processor

Summary

This document outlines the development and implementation of a simulator designed to allow users of the PDP-8 Floating Point System to leverage the speed and precision of the DEC FPP-12 Floating Point Processor without needing to rewrite existing computer programs.

Key details include:

• Performance: The simulator provides significantly faster execution rates—approximately 6 times faster for single instructions like FADD and 10 times faster for complex functions—compared to conventional software packages, while also offering 48-bit precision.

• Architecture: The system consists of three primary components:

  1. FPPSIM: The basic simulator unit that translates software floating-point instructions into a format compatible with the FPP-12.
  2. PTCHSIM: A patch unit allowing for the addition of custom routines and user-defined functions.
  3. IOCNTRL: An I/O controller providing formatted floating-point output.

• Operational Usage: The document provides instructions on the assembly and integration of these units, memory and core requirements, and detailed classifications of the supported instruction set (including entering/exiting the simulator, memory reference, and specific function modes).

• Validation: The authors report successful testing in various real-time and data analysis applications, noting a substantial reduction in computing time (e.g., a process taking one hour was reduced to seven minutes) and successful adoption in laboratory research environments.