Pdp-12 Kw12a Clock Test

Summary

This document is a technical manual and diagnostic program listing for the KW12A Real Time Clock Test for the PDP-12 computer. Created in June 1970, the diagnostic is designed to verify the correct operation of the KW12A hardware, including registers, clock control, and input channels.

Key components include:

• Purpose: It ensures the KW12A components (Buffer Preset Register, Clock Enable Register, Clock I/O Interface, and External Input Channels) are functioning correctly.
• Requirements: The test requires a PDP-12 with the KW12A installed, an AD12 Analog-to-Digital Converter (for optional fast sample testing), and an ASR-33 Teletype or equivalent.
• Operational Details: The program occupies memory locations 0000 to 7600 and must be loaded using the binary loader. The manual provides specific loading procedures, switch settings for various test configurations, and an error handling guide.
• Error Reporting: The document includes an extensive list of error messages (e.g., "CLAB FAILED," "INTERRUPT FAILED," "RATE FAILS"), which help operators identify specific hardware failures by referencing test numbers.
• Technical Listing: The majority of the document comprises the assembly code (PAL10) for the diagnostic, including cross-references, constants, and detailed test logic used for troubleshooting the KW12A.