Pdp-12 Checkerboard

Summary

The "Pdp-12 Checkerboard" is a diagnostic program designed by Harold Long (Digital Equipment Corporation, 1969) to verify the operational integrity of PDP-12 computer memory, ranging from 4K to 32K.

Key Technical Details:

• Methodology: The program performs memory reliability testing using "read-modify-write" cycles. It writes data to memory cells, reads them back, and compares the contents against the expected values (specifically 5252 and 6525) to ensure stability and proper read/write response.
• Error Detection: If a mismatch occurs, the program provides an error report via a connected ASR-33 teletype. This output includes the memory field, the specific address, the expected accumulator content, and the actual content found in the memory location.

• User Controls: The program offers various switch-selectable options for the operator, including:

  • Suppression of halts or printouts during errors.
  • The ability to loop on a specific failing memory cell for troubleshooting.
  • Limiting testing to a specific memory field.
  • Dumping the pass counter or inhibiting the audible bell signal at the end of a pass.

• Requirements: The program requires a PDP-12 computer, an ASR-33 teletype (or equivalent), and a functioning binary loader to initiate the test.