Pdp-8, 8/I Memory Parity Checkerboard

This document describes the "PDP-8, 8/I Memory Parity Checkerboard" diagnostic program, created on May 14, 1968, by the Digital Equipment Corporation Diagnostics Group.

Purpose: The diagnostic is designed to test the parity bit plane for core failure in PDP-8 or 8/I computers, specifically under worst-case, half-selected line conditions within a 4K memory system.

Key Technical Details:

• Versions: The program exists in two versions: "Low End" (occupying memory locations 0005–0146 octal) and "High End" (occupying locations 7430–7571 octal).
• Operation: The diagnostic writes checkerboard patterns into the parity bit plane. It reads a location to verify parity; if no parity error occurs, it complements the word and writes it back to re-verify.
• Error Handling: The program halts upon detecting an error. It provides two error halt points per test: one to display the contents of the faulty memory location and another to display the specific memory address where the parity error occurred. Operators can use the "CONTINUE" command to clear errors and resume testing.
• Setup: The program is loaded via a RIM loader. The user must configure specific switch register settings (e.g., 0100 for standard PDP-8 units, 0101 for standard PDP-8/I units) to determine the memory pattern before beginning the test.

The remainder of the document provides the full assembly code listing and symbol tables for both the Low End and High End diagnostic programs.