System Reference Manual

This "VAXBI System Reference Manual" serves as a comprehensive technical guide for designers developing components for the VAXBI bus. It thoroughly defines all aspects of the VAXBI system, including its electrical characteristics, mechanical requirements, logical bus protocol, and system architectural demands, all aimed at ensuring compatibility and extensibility.

The document is structured into four main parts:

1. Bus Description and Requirements: This section introduces the VAXBI bus as a 32-bit synchronous, wire-ORed interconnect for processors, memories, and I/O devices (nodes). It details the bus's 30-bit address space (1 gigabyte, split into memory and I/O, with specific allocations for nodespace, windows, and multicast), its peak data transfer rate of up to 13.3 megabytes per second, and its 52 signal lines (categorized into data path, synchronous control, clock, and asynchronous control). It outlines the distributed arbitration scheme, various transaction types (single and multi-responder, data transfer, interprocessor communication, diagnostics), caching protocols, and system/node initialization procedures and their timing. It also defines the numerous VAXBI registers for control, status, and error reporting, and categorizes VAXBI nodes into processors, memories, and adapters, specifying the transactional requirements for each.

2. The BIIC (Bus Interconnect Interface Chip): This part focuses on the BIIC, a custom integrated circuit that acts as the primary interface between the VAXBI bus and the node's user logic. It describes the BIIC's features, its interface signals (BCI signals) that connect to the node's internal logic, its master, slave, and interrupt functions, and the operation of its internal registers. The BIIC also provides extensive diagnostic facilities, including self-test, error detection (parity, protocol checking), and error recovery mechanisms. Electrical specifications and packaging information for the BIIC are also detailed.

3. Bus Support Components: This section provides specifications for key supporting hardware, including the VAXBI clock driver and clock receiver, detailing their electrical characteristics and pin assignments.

4. Application Notes: This part offers practical guidance and deeper insights into various topics, such as different types of adapters and their functionalities, design considerations for main memory and caching (including write-through and write-back caches), recommended usage strategies for BIIC registers, detailed self-test operations and reporting, the use of the RETRY response code to manage bus access and timeouts, and specifics on clock system design and power sequence timing from the BCI viewpoint.

Appendices further elaborate on specific topics like the BDCST transaction, wired-OR transmission line effects, responses to exception conditions, allowed exceptions to VAXBI requirements for specific components, and device type code assignment procedures.

In essence, the manual provides a complete blueprint for designing and implementing compatible and reliable VAXBI-based systems and modules, covering everything from high-level architectural concepts to low-level electrical and mechanical specifications.