DWLPA and DWLPB PCI Adapter

This document is a technical manual for the DWLPA and DWLPB PCI adapters (PCIA), designed for Digital AlphaServer 8200 and 8400 I/O subsystems using the TLSB I/O hose interface.

The PCIA acts as a bridge, providing a complete PCI and EISA bus subsystem. Key features include:

• Compatibility: Architecturally and hardware compatible with existing CPU-PCI and PCI-EISA bridges and the TLSB hose protocol.
• Configurability: Offers 12 PCI expansion slots plus a dedicated slot for the PCI-EISA bridge module (KFE70), which provides access to an 8-slot EISA bus.
• Performance: Implements three physically separate 33 MHz PCI buses (each with 4 slots) for improved DMA throughput, an on-chip scatter/gather cache, and support for prefetching host memory blocks. DWLPA supports a 32K-entry scatter/gather map RAM, while DWLPB supports a 128K-entry RAM for PCI-to-TLSB address translation.
• Addressing: Supports dense mapping for cache-block sized bursts and sparse mapping for byte-level access across PCI memory, I/O, and configuration spaces, with CPU-to-PCI and PCI-to-System Bus translation. It does not support PCI cache coherency or 64-bit PCI addressing/data paths.
• Communication: Handles four types of transactions: DMA, mailbox, CSR (Control and Status Register), and interrupt, facilitated by High-Performance Controllers (HPCs) that manage each physical PCI bus.
• Registers: A comprehensive set of registers (e.g., CTLx, MRETRYx, ERRx, IMASKx, WBASE_xx) controls PCIA functionality, arbitration, addressing windows, interrupts, and diagnostics.
• Error Handling: Categorizes errors as fatal (requiring PCIA reset) and nonfatal (generating interrupts), covering various types of errors across Down Hose, Mailbox, CSR, DMA, PCI, and PCIA operations.
• EISA Bridge: The integrated KFE70 module (Intel PCEB/ESC chipset) provides the EISA bus, managing address mapping, buffering, and interrupt consolidation via 8259 controllers.

The document details the functional descriptions of PCI interface operations (CPU-initiated and device-initiated cycles), including address/data phases, transaction termination, and exclusive access support. It also describes the "Hose" interface, which transfers data between the I/O port and the PCIA, and how interrupts are handled and prioritized.