Rawhide Bus Spec

This document, "Rawhide Bus Spec Revision 1.1," details the architecture and operational specifications of the Rawhide System's primary interconnect, the MCBus (Module/Memory Connection Bus). Dated May 1, 1995, it serves as a confidential technical guide for system components and transactions.

The Rawhide system utilizes the MCBus as a synchronous interconnect to connect various building blocks on a motherboard, including CUDs (CPU Daughtercards), IODs (IO Daughtercards), local memory modules (SDSIMMs/ADSIMMs), and a GCD (Global Connection Interface). The GCD further connects to the GCBus (Global Connection Bus).

Key aspects covered include:

• System Architecture: The MCBus supports configurations of up to 4 CUDs, 4 IODs (max 6 combined), 4 pairs of memory modules, and 1 GCD, with up to 8 nodes on the GCBus.
• Data Transfer: Data is transferred in 4 consecutive 15ns cycles during Read, Write, or Fill transactions, with potential dead cycles to manage tri-state turnoff/turnon.
• Addressing Scheme: Defines distinct Memory Space (cacheable, MCADR<39>=0) and IO Space (non-cacheable, MCADR<39>=1) addressing, including node ID assignments (MID, GID, RID) and data wrapping.
• Arbitration: A central arbiter on the motherboard manages MCBus access using a mix of Round-robin, fixed priority, bus hold, and bus parking, with specific priority schemes for IIP and PIO motherboards. Additional features include bus parking and a lockout mechanism to prevent node starvation.
• Transactions: Detailed descriptions of numerous MCBus transactions for memory (e.g., Read0/1-Mem, ReadMod0/1-Mem, WriteThru-Mem, WriteBack-Mem, WriteFull-Mem, WritePart-Mem, WriteMerge-Mem, Invalidate, SetDirty, ReadFill0/1) and I/O (e.g., Read0/1-IO, ReadPeer0/1-IO, WriteThru-IO, WriteIntr-IO, WriteMask-IO). These sections explain their purpose, cache coherence implications, and command/address signal usage.
• Interrupts: MCBus Interrupts (I/O Generated, Node Halt, Interval Timer, Inter-processor) are implemented using WriteIntr-IO and WriteThru-IO transactions.
• Signals: A comprehensive list and description of MCBus signals (output, input, bi-directional) covering command, address, data, control, and status. This includes MCCMD, MCADR, MCDAT (128-bit datapath), MCCHK (ECC codes), MCBMSK (byte masks), MCCNFL (confirmation), MCREQL (request), MCGRANT_L (grant), and various stall/hold signals.
• Timing Specifications: Provides estimated setup and clock-to-output times for key MCBus signals, emphasizing the synchronous nature of the bus with a reference clock up to 66 MHz.

The document outlines the protocol for inter-module communication, data integrity (ECC), and cache coherency within the Rawhide system, along with constraints on multiple outstanding transactions.