VAX/VMS Device Driver I/O Architecture

This training module provides an introduction to the hardware components and architecture of the VAX/VMS I/O system, specifically for the VAX-11/780, VAX-11/750, and VAX-11/730 processors. It explains how peripheral devices connect to adapters (UNIBUS and MASSBUS), which then interface with the CPU and memory controllers through the Synchronous Backplane Interconnect (SBI) bus. The document details the physical address space for different VAX models and the critical process of address translation between UNIBUS/MASSBUS and SBI addresses. It differentiates between direct and buffered data paths, outlining their performance characteristics, use cases, and constraints for data transfer. Key areas covered include SBI bus arbitration, priority access, interrupt dispatching using the System Control Block (SCB), and the operational specifics, internal registers, and address mapping of both the UNIBUS Adapter (UBA) and the MASSBUS Adapter (MBA). The module aims to equip readers with the knowledge to understand the system's hardware architecture, address translation mechanisms, and appropriate data path selection.