VAX 11/780 Architecture Handbook

This document is "VAX-11/780 ARCHITECTURE HANDBOOK VOL. 1 (1977-78)," a foundational guide detailing the architecture of the VAX-11/780 computer system, primarily for assembly language programmers working with non-privileged code.

The VAX-11/780 is presented as Digital Equipment Corporation's most powerful system in the -11 family, designed for high-performance virtual memory applications across scientific, timesharing, and commercial domains. Its architecture, "Virtual Address eXtension" (VAX), was a co-design between hardware and software engineers, aiming for significant enhancement to virtual addressing, small code size, and compatibility with the PDP-11 series. User-level PDP-11 programs can execute in a Compatibility Mode, while VAX/VMS operating system services run in Native Mode.

Key architectural features detailed in this volume include:

1. Virtual Memory: A vast 4-billion-byte virtual address space (32-bit addressing), managed by full demand paging, supporting concepts like working sets, balance sets, and memory swapping. It emphasizes page-level protection and sharing.
2. Instruction Set: A powerful, orthogonal, and variable-length instruction set of 244 basic instructions. It supports a wide range of data types, including various integer sizes (byte, word, longword, quadword), floating-point and double floating-point numbers, character strings, packed decimal strings, and variable-length bit fields. Native Mode instructions include specialized operations for arithmetic, string manipulation, and direct implementations of higher-level language constructs.
3. Addressing Modes: An elegant and flexible set of addressing modes (e.g., register, immediate, displacement, indexed, autoincrement/decrement, PC-relative for Position Independent Code) that interact with 16 32-bit general-purpose registers (including dedicated registers like PC, SP, FP, AP).
4. Registers and Stacks: The system utilizes 16 general-purpose registers and a sophisticated stack mechanism with multiple stacks tailored for different access modes (kernel, executive, supervisor, user) and a dedicated interrupt stack, managed by the Stack Pointer (R14).
5. Hardware Architecture: The system comprises a Central Processing Unit (CPU), memory subsystem, I/O subsystems, and a console subsystem, all connected via the high-speed Synchronous Backplane Interconnect (SBI). The CPU incorporates an 8KB memory cache, an 8-byte instruction buffer, and a 128-entry address translation buffer for performance optimization. The memory subsystem uses ECC MOS memory for data integrity. I/O is facilitated through UNIBUS and MASSBUS adaptors.
6. Reliability, Availability, Maintainability (RAMP): A core design philosophy for the VAX-11/780. RAMP features include hardware "firewalls" (memory access modes), extensive error checking (e.g., arithmetic traps, Cyclic Redundancy Check), special instructions, robust diagnostic aids (e.g., real-time clock, SBI history silo, remote diagnosis), and software architecture for system consistency, error logging, and automatic restart.

The handbook systematically covers instruction formats, operand specifier notation, data representation, and provides detailed descriptions of instruction classes such as integer and floating-point operations, special instructions (e.g., register manipulation, queue operations, bit-field processing, array indexing), control instructions (branching, jumping, subroutine and procedure calls), character string operations, and decimal string operations. It also extensively explains exception handling (traps, faults, aborts), tracing mechanisms, serious system failures, and privileged instructions that allow controlled access to system-level operations and processor registers.