CVAX CPU Chip Engineering Specification DC 341

This document is the CVAX CPU Chip Engineering Specification, detailing the external interface and behavior of the CVAX CPU chip.

Key Information:

• Chip Type: The CVAX CPU is a 32-bit, virtual memory microprocessor implemented in CMOS I (double metal CMOS). It functions as a MicroVAX central processor designed for high performance and low cost in single-board computers, workstations, and low-end systems.
• Architecture Subset: It implements a subset of the full VAX architecture, focusing on the external interface rather than internal organization.

• Key Features:

  • Data Types & Instruction Set: Supports a subset of VAX data types (byte, word, longword, quadword, character string, variable-length bit field) and instructions (integer, logical, address, control, procedure call, queue, OS support). Floating-point operations are handled by an external coprocessor, and other omitted VAX features can be supported via macrocode emulation.
  • Memory Management: Includes a full VAX-compatible demand-paged memory management unit on-chip.
  • Cache: Features a 1KB on-chip cache configurable for I-stream only or both I-stream and D-stream references.
  • Address Space: Supports 4 gigabytes of virtual memory and 1 gigabyte of physical memory.
  • Performance: Achieves a 100 nsec microcycle and a 200 nsec I/O cycle at maximum frequency.
  • Packaging: Comes in a standard 84-pin surface-mounted chip carrier.

• Differences from Full VAX Architecture:

  • Omits certain data types (decimal string, octaword, hfloating) and instruction classes (many character/decimal string, EDITPC, CRC, compatibility mode, hfloating), though microcode assists and external FPUs provide support.
  • Excludes some internal processor registers (e.g., RICR, ICR, TODR), which can be externally supported.
  • Does not have a built-in console function.