Core Fundamentals Tom Hughes

This document, "Core Fundamentals," by Tom Hughes, provides an in-depth explanation of core memory principles, focusing on a 2D memory system and contrasting it with conventional 3D systems. It begins by describing ferrite cores as toroidal (donut-shaped) with specific dimensions (e.g., 0.30" outer diameter, 0.20" inner diameter, 0.007" height) and their crucial "square loop characteristics" for minimizing noise.

The document elaborates on the core's magnetic behavior using the B/H (hysteresis) loop. It explains how applying current in the "write" direction causes flux changes. A "half select current" leads to reversible flux changes, while a "full select current" causes irreversible changes, switching the core from a '0' to a '1' state and generating a voltage output on the sense winding. Key timing parameters, "peaking time" and "switching time," are defined in relation to this output. A "read cycle" involves current in the opposite direction, switching from a '1' to a '0' state and inducing a signal of opposite polarity. The document also notes that temperature affects the B/H loop, necessitating current amplitude adjustments.

In stacked arrays, a "coincident current technique" is employed for 4K memories (4,096 cores in a 64x64 array). Half current is passed through horizontal and vertical drive lines; only the core at their intersection receives full select current and switches. In 3D systems, an "inhibit winding" is used to write a '0' by applying opposing half-current. However, in 2D systems, an alternative is used where one X or Y line is not activated, causing the core to see only a half-select current.

A significant challenge in core memories is noise from "half-disturbed" cores (those receiving only half current). To mitigate this, the sense winding is typically threaded through half the cores in one direction and the other half in the opposite direction, causing opposing polarity signals to cancel out. The concept of a "Worst Case Pattern (WCP)" is introduced, where slight differences between half-disturbed '1's and '0's create "DELTA NOISE," which can be additive to legitimate signals, making '0' outputs harder to distinguish.

To optimize reading and reduce noise, especially from the digit drive (which generates most of the noise), a "stagger" technique is used: the digit read current is turned on 75 ns before the word read current, allowing the digit noise to decay before the core begins switching.

The 2D memory organization features X (word) and Y (digit/bit) dimensions, with the Y dimension serving a dual function for both address and data. Each bit is physically arranged in a 16x512 configuration to balance electrical line length. "Word current phasing" allows 256 lines to drive 512 addresses by using current direction to select between two cores at each intersection (one additive, one subtractive). Decoding further segments the 256 lines into a 16x16 matrix, with an additional "MA BIT 5" for phasing to address upper or lower 4K blocks.

Finally, the document discusses memory cycles, explaining that this system operates on a "read-pause-write" cycle due to the absence of a memory buffer. This fixed pause, typically 300 ns, accounts for cable delays to/from the Central Processor (CP) and any data modification time.