Introduction to the COMET Microarchitecture

This document provides an introduction to the COMET Microarchitecture, a microprogrammable computer designed specifically to emulate the VAX-11 architecture. Written in March 1980 by Yale N. Patt, it aims to explain COMET's internal workings for those interested in its VAX implementation and for microcode development. It is explicitly not a general microprogramming text or a hardware reference manual.

Key aspects of the COMET microarchitecture include:

1. Overall Design: COMET consists of an 80-bit microinstruction control store (up to 16K words), a microsequencer, a 32-bit Data Path, and various registers. It communicates via internal buses (WBUS, MBUS, RBUS) and operates on a basic 320 nanosecond microcycle.

2. Microsequencer: Unlike systems with a dedicated microprogram counter, COMET's next microinstruction address (CSA) is determined in three ways:

   • Multi-way Conditional Branching: By logically ORing bits from the current microinstruction's NEXT field with specific internal signals (e.g., from VAX registers, buses, or flag bits) controlled by the BUT field.
   • Microstack: A 16-deep stack (USTK) is used for nested subroutine calls, with addresses pushed by JSR/PUSH and popped by BUT/RETURN micro-orders.
   • VAX-specific ROMs: The IRD1 and IRDX ROMs provide starting addresses for VAX instruction emulation and operand evaluation, respectively, indexed by VAX opcodes and internal status.

3. Data Path: This is the computational core, featuring:

   • ALU (Arithmetic Logic Unit): Performs arithmetic, BCD, and logical operations. Its inputs and outputs are highly multiplexed and can be shifted or rotated, controlled by various fields (MUX, ALU, DQ, ALUSHF, ALUCI). Special functions are grouped under the ALPCTL field.
   • Super Rotator: A powerful combinational logic circuit for efficient bit manipulation (e.g., barrel shifting, field extraction, data format conversion, rotation). It also generates 2-bit status codes (SRKSTA) used for microsequencer branching.
   • Scratch Pad Registers: A set of 64 fast-access 32-bit registers (48 R-type, 16 M-type) and a Long Literal Register are used for storing intermediate results, constants, and emulating VAX general-purpose and internal processor registers. The Register Back Up Stack (RBS) saves VAX register state during operand evaluation for interrupt recovery.

4. VAX-11 Emulation Implementation:

   • Instruction Execution: VAX instruction emulation is initiated by the BUT/IRD1 micro-order, which calls a hardware routine (DOSERVICE) to check for pending traps/interrupts before fetching the next VAX instruction opcode.
   • Interrupts and Exceptions: COMET handles VAX interrupts (external events) and exceptions (internal process faults) through specialized microcode routines. Detection occurs via hardware-triggered microtraps (which force a branch to a fixed address and typically save the current microinstruction for re-execution after the fault is corrected), microprogrammed conditional branches, or ROM decodes. The process involves saving the VAX machine state (PC, PSL) on appropriate stacks and transitioning to service routines.
   • Memory Management: COMET implements VAX's virtual memory system, including Page Table Entries (PTEs) and a Translation Buffer (TB). Microtraps are used to handle memory management faults such as unaligned accesses, TB misses, and Access Control Violations (ACV) or Translation Not Valid (TNV) errors, ensuring data integrity and correct program flow.

5. User Microprogramming: COMET offers features to support user-defined microcode, enabling instruction set enhancements and performance tuning. The 80-bit microinstruction provides significant parallelism, allowing multiple operations (e.g., ALU function, memory access, and conditional branching) to occur simultaneously within a single microcycle.

The document concludes with detailed examples of microprogramming, including the emulation flow for a VAX INDEX instruction and the design considerations for a new user-defined instruction, demonstrating how COMET's microarchitecture features are leveraged for efficient execution.