KA655 CPU Module Technical Manual

This document is the KA655 CPU Module Technical Manual, order number EK-KA655-TM-001, published by Digital Equipment Corporation in January 1989.

Purpose: The manual documents the functional, physical, and environmental characteristics of the KA655 CPU module and the MS650-BA memory expansion module. It also covers the KA655-BA CPU module (functionally equivalent but without multiuser VMS and ULTRIX licenses) and is intended for design engineers and application programmers familiar with DIGITAL's Q22-bus and the VAX instruction set. It should be used alongside the VAX Architecture Reference Manual.

Overview of the KA655 CPU Module: The KA655 is a quad-height VAX processor module for the Q22-bus (extended LSI-11 bus), designed for high-speed, real-time, and multiuser/multitasking environments. It features a two-level cache for performance optimization and can support up to four MS650-BA memory modules (16 Mbyte, 360 ns, ECC memory). Communication with the console device is via the H3600-SA CPU cover panel, which includes configuration switches and an LED display.

Key Components and Features:

• Clock Functions (1.2): Implemented by a CVAX clock chip, generating MOS and auxiliary clocks, and synchronizing reset and data signals.
• Central Processing Unit (CPU) (1.3): Implemented by the CVAX chip (approx. 180,000 transistors), featuring a 60 ns microcycle and 120 ns bus cycle at 33 MHz. It supports full VAX memory management, a 4 GB virtual address space, VAX general purpose registers (GPRs), system registers, a 1 Kbyte first-level cache, and a 28-entry translation buffer. It fetches and executes VAX instructions, passing floating-point instructions to the CFPA chip.
• Floating-Point Accelerator (1.4): Implemented by the CFPA chip (approx. 60,000 transistors), executing 70 floating-point instructions.

• Cache Memory (1.5): Two-level cache:

  • First-level cache: 1 Kbyte, two-way associative, write-through, 60 ns cycle time (within CVAX chip).
  • Second-level cache: 64 Kbyte, direct-mapped, write-through, 120 ns cycle time for longword, 180 ns for quadword (uses 16K by 4-bit static RAMs).

• Memory Controller (1.6): Implemented by the CMCTL VLSI chip (approx. 25,000 transistors), supporting up to 64 Mbytes of 360 ns ECC memory via MS650-BA modules.

• MicroVAX System Support Functions (1.7): Implemented by the SSC chip (approx. 83,000 transistors), providing console and boot code support, operating system support, timers, battery-backed RAM, halt arbitration, console serial line, and programmable timers.
• Resident Firmware (1.8): 128 Kbytes of 16-bit ROM providing board initialization, power-up self-tests, console emulation, booting from Q22-bus devices, multilingual support, and configuration/programming utilities.
• Q22-bus Interface (1.9): Implemented by the CQBIC chip (approx. 40,870 transistors), supporting up to 16-word block mode transfers, a 16-entry map cache for address translation, interrupt arbitration logic, and Q22-bus termination.

Manual Organization:

• Chapter 1: Overview: Introduces the KA655 CPU and MS650 memory modules, highlighting features and specifications.
• Chapter 2: Installation and Configuration: Details the installation and configuration of the KA655 and MS650-BA modules in Q22-bus backplanes and system enclosures, including connector pinouts and configuration options via the H3600-SA CPU cover panel or KA630CNF configuration board.
• Chapter 3: Architecture: Describes the KA655's registers, instruction set, and memory architecture, including detailed sections on the Central Processor (Processor State, Memory Management, Exceptions and Interrupts, CPU References), Floating-Point Accelerator, Cache Memory (First-Level and Second-Level), Main Memory System, Console Serial Line, Time-of-Year Clock and Timers, Boot and Diagnostic Facility, and Q22-bus Interface.
• Chapter 4: KA655 Firmware: Covers the functional operation of the KA655 firmware, including entry/dispatch code, boot diagnostics, device booting sequence, console program, and console commands.
• Appendix A: KA655 Specifications: Provides physical, electrical, and environmental specifications.
• Appendix B: Address Assignments: Maps the VAX memory space.
• Appendix C: Q22-bus Specification: Describes the Q22-bus, its signals, data transfer cycles, and electrical characteristics.
• Appendix D: Acronyms: Lists acronyms used in the manual.