Preliminary Engineering Specification for the KA650-AA Processor Module

This document is a Preliminary Engineering Specification for the KA650-AA Processor Module, dated April 18, 1986, by Gary Lidington of Digital Equipment Corporation. It is marked "RESTRICTED DISTRIBUTION" and "COMPANY CONFIDENTIAL."

The specification details the functional, physical, and environmental characteristics of the KA650-AA Processor Module, serving as a comprehensive programmer's reference in conjunction with the VAX Architecture Standard.

Key aspects of the KA650-AA Module:

• Core Functionality: It forms a VAX CPU/Memory subsystem, designed to work with MS650 memory expansion modules (supporting up to 64MB of ECC memory).
• Configuration: The KA650-AA can be configured as either an arbiter CPU (managing Q22-Bus mastership and interrupts) or an auxiliary CPU in multi-processor systems.
• Performance: Estimated to be 2.5 times faster than a VAX 11/780.
• Key Components (implemented with in-house VLSI chips):
  • A VAX Central Processor (CVAX chip) supporting the MicroVAX instruction set, full VAX memory management (4GB virtual memory, demand paging).
  • A Floating Point Accelerator (CFPA chip) for VAX floating-point instructions and accelerated integer operations.
  • A Two-Level Cache System including a 1KB, 100ns first-level cache and a 64KB, 200ns second-level cache, both with parity protection.
  • A Main Memory Controller (CMCTL chip) supporting 400ns ECC memory on up to four MS650 modules.
  • Integrated Processor Clock Registers (Time of Year, Interval, Programmable Timers).
  • A Boot and Diagnostic Facility with on-board LEDs, external display/switches, and 64KB ROM for initialization, console emulation, self-tests, and booting.
  • A Q22-Bus Interface (CQBIC chip) handling block transfers, 22-bit to 29-bit address translation via a 16-entry map cache, interrupt arbitration (BR7-BR4), and interprocessor communication.

The document also provides summaries of the MS650 memory modules (8MB and 16MB options), detailed information on processor state, instruction set, memory management, exceptions/interrupts, various registers, main memory organization, console serial line, and extensive appendices covering physical/electrical specifications, environmental/reliability data, address assignments, instruction set details, and error matrices.