NVAX Plus CPU Chip Functional Specification

This document is the "NVAX Plus CPU Chip Functional Specification," Revision 0.3, dated October 1991. It is marked as "DIGITAL CONFIDENTIAL" and describes the NVAX Plus CPU chip developed by the Semiconductor Engineering Group of Digital Equipment Corporation.

The NVAX Plus CPU Chip is a high-performance, single-chip implementation of the VAX Architecture designed for use in low-end and mid-range computer systems. Key features and components include:

• Architecture: It is partitioned into multiple sections (IBOX, EBOX, MBOX, FBOX, Interrupt sections, and CBOX) that cooperate to execute the VAX base instruction group.
• Memory Subsystem: The chip integrates the first levels of the memory subsystem hierarchy, including an on-chip virtual instruction cache and an on-chip physical instruction and data cache. It also incorporates a controller for a large second-level cache implemented using static RAMs on the CPU module.
• External Interface: The NVAX Plus chip features an NVAX core with an EVAX external interface. Microcode changes were implemented to support EVAX interlocks and startup from serial ROM.
• Memory Management: Cache fills and coherency transactions are controlled by the EDAL system logic, allowing only one CPU request to be active at a time.
• Performance: It is a CMOS-4 macropipelined design, with a typical cycle time of 14 ns, capable of operating at slower or faster cycle times, making it suitable for a wide range of systems from workstations to multiprocessor servers.

The specification details the chip's operation, including its architectural summary, external interface, instruction pipeline, error handling, chip initialization, and testability features. This particular document is the third external release of the specification.