Introduction to Designing a System- with the DECchip ™ 21064 Microprocessor

This document, an application note from Digital Equipment Corporation, introduces the principles of designing a system with the DECchip 21064 Microprocessor.

Key aspects covered include:

1. System Integration & Architecture: It describes how to integrate the 21064 chip, detailing its reaction to reset, interface signal control, and overall system structure, which typically includes the processor, system control logic, and an optional (but performance-enhancing) external backup cache (Bcache).
2. Chip Configuration & Booting: The document explains critical initial setup like power supply requirements (3.3V), input voltage levels (vRef), and clock signals (differential, pseudo-ECL). It also details the flexible bootstrapping process via a serial ROM (SROM) and how external interface parameters (e.g., data bus width, clock division, clock delay) are configured using interrupt lines during reset.
3. Cache and Memory Interface: A significant portion focuses on the Bcache, explaining its organization (32-byte blocks, parity/ECC) and how its timing for reads and writes is programmable through an internal processor register (BIU_CTL IPR). It differentiates between CPU-controlled Bcache accesses (hits) and system logic-controlled external cycles (misses, fills, victim writes, DMA).
4. Data Transfer and Control: It illustrates various memory operations, including READBLOCK and WRITEBLOCK cycles, non-cacheable memory writes, and special atomic operations like Load Locked/Store Conditional, emphasizing the responsibilities of external system logic in these scenarios.
5. DMA and I/O: The document briefly discusses Direct Memory Access (DMA) and I/O interfacing, including methods for external devices to access the cache/memory subsystem and general approaches to I/O control.

The overarching goal is to provide design engineers with sufficient information to understand the fundamental concepts and challenges involved in building a functional 21064-based computing system, highlighting the chip's flexibility and programmability.