DECchip 21064-AA Microprocessor Product Brief

The DECchip 21064-AA, introduced in July 1992, is the first microprocessor implementing Digital's 64-bit Alpha architecture. It is a .75 micron CMOS-based, super-scalar, super-pipelined RISC processor designed for high performance, multiple instruction issue, and multiprocessor support, aiding software migration from VAX/VMS and MIPS/ULTRIX environments.

Key Features:

• Architecture: Full 64-bit Alpha RISC architecture optimized for high-performance implementations, supporting multiprocessor systems and various data types (IEEE and VAX floating-point).
• Performance: Operates at 150 MHz, featuring a dual-pipelined design capable of dual instruction issue and a peak execution rate of 300 million operations per second. It emphasizes high speed without pipeline hazards like load or branch delay slots.
• On-Chip Components: Includes an 8KB direct-mapped data cache (write-through) and an 8KB direct-mapped instruction cache, a pipelined floating-point unit, an on-chip write buffer with four 32-byte entries, and a demand-paged memory management unit (MMU) with separate I-stream and D-stream Translation Buffers (TBs).
• Memory & I/O: Supports external cache memory (0-8MB) with on-chip control, offers selectable 64 or 128-bit data bus widths (75 MHz to 18.75 MHz), and incorporates on-chip parity and ECC generators/checkers. It provides a 64-bit virtual address space (implementing a 43-bit subset) and supports a 16GB physical address space.
• Instruction Set & Software: Uses a fixed 32-bit instruction size with separate 32-entry 64-bit integer and floating-point register files. It leverages Privileged Architecture Library Code (PALcode), a flexible software layer for operating system-specific functions, memory management, and atomic operations, enabling support for multiple OS environments.
• Differentiators from Conventional RISC: Offers true 64-bit architecture (not an expansion of 32-bit), flexible read/write ordering for multiprocessor scalability, efficient 64-bit byte manipulation (avoiding read-modify-write cycles), and imprecise arithmetic traps by default for performance (with optional precise traps via trap barriers). It also includes software-controlled "HINTS" for hardware optimization.
• Physical Characteristics: Operates at 3.3 volts, with a typical power dissipation of 23W (27.5W maximum).