DECChip 21064-AA RISC Microprocessor Preliminary Data Sheet

This document is a Preliminary Data Sheet for the DECchip™ 21064-AA RISC Microprocessor, the first implementation of the Digital Equipment Corporation Alpha architecture.

The 21064-AA is a CMOS-4 (.75 micron) super-scalar, super-pipelined CPU designed for a wide range of systems, from uniprocessor workstations to midrange multiprocessors.

Key aspects described include:

• Microarchitecture: Detailed breakdown of its independent execution units (Ebox for integer, Fbox for floating point, Abox for address/memory management, Ibox for central control and instruction issue). It supports dual instruction issue per cycle for high performance.
• On-Chip Components: Features 8KB data and instruction caches, a multi-entry I-stream (Instruction Translation Buffer) and D-stream (Data Translation Buffer) for memory management (filled and maintained by PALcode), an on-chip write buffer, and performance counters.
• Privileged Architecture Library (PALcode): Explains how PALcode implements complex architectural functions (e.g., translation buffer fills, interrupt handling, exceptions) that are not directly in hardware, defining the processor's behavior in privileged modes.
• External Interface: Details the chip's connection to an external cache, its programmable bus interface unit (BIU) supporting 64-bit or 128-bit data bus modes, signal definitions, clocking schemes, and various transaction types (e.g., READBLOCK, WRITEBLOCK, FETCH).
• Electrical Characteristics: Provides DC and AC specifications, including power supply requirements (supporting CMOS/TTL and ECL 100K modes), input/output signal levels, and power dissipation figures.
• Physical Information: Includes package dimensions and a detailed pinout list for the 431-pin PGA.

Important Errata: Revision AA of the DECchip 21064 does not fully support PALcode routines for correcting all ECC errors reported on data from Load instructions. While errors are detected, the necessary state for complete correction is not always maintained. This issue is planned for correction in a future revision, and systems using parity protection are unaffected.