MB20 Internal Memory Unit Description

This document, EK-MB020-UD-001, describes the MB20 Internal Memory Unit, an internal memory system designed for the KL10 computer.

1. Overview:

• Purpose: The MB20 allows the MBox (main processor unit) to access one to four data words per memory reference.
• Architecture: It consists of one to four memory controllers, each managing one to four ferrite core storage modules (SMs). SMs have a capacity of 32K (32,768) 37-bit words (36 data, 1 parity). A fully configured system can have up to 16 SMs, totaling 512K words.

• Basic Operations: The MB20 supports standard memory operations:

  • Write: Data is transferred from the MBox to core memory.
  • Read: Data is transferred from core memory to the MBox.
  • Read-Modify-Write (RMW): Data is read from core, modified by the MBox, and then written back to the same core location.
  • Diagnostic Cycle: Allows program control to load configuration (e.g., interleave mode, address boundaries) and read status information from the controller.

• Memory Access: Uses a "start/acknowledge" (START/ACKN) system. Memory references access "quad-words" (groups of four words). Specific words within a quad-word are selected using Request (RQ 0-3) lines, while Address (ADR) lines specify the quad-word location and starting address. Data transfer for multi-word requests is serial.

• Interleaving: Enhances performance by allowing two controllers on the same SBus (system bus) to operate simultaneously.

  • 4-Way Interleave (Normal KL10 mode): Two SMs per controller operate in parallel, allowing four core locations to be accessed concurrently. One controller handles even addresses, the other handles odd.
  • 2-Way Interleave: One SM per controller operates in parallel, accessing two core locations.
  • No-Interleave: A single controller accesses one SM.

• Addressing & Configuration: Address boundary registers (set via diagnostic cycle) define the accessible memory space for each controller. Request enable levels (RQ EN) specify which odd/even addresses a controller responds to.

• Error Checking: The system checks for address parity errors, data parity errors, and non-existent memory (timeout for no ACKN). Incomplete requests (hung conditions) are also detected. Errors are flagged, can cause interrupts (APR), and failing addresses are stored.
• Diagnostic Features: Include a "loop-around mode" to test the data path without actual core R/W operations, and "margin control" to test SM operation under varied X-Y select current amplitudes, sense strobe timing, and sense amplifier threshold voltages.

2. Functional Description (Detailed Operations):

• SBus (System Bus) Operation: The SBus connects memory units to the MBox. It uses continuous clock signals (SBUS CLK INT) for synchronization, and multiple START, ACKN, and DATA VALID lines to speed up transfers.
• Memory Addressing (Detailed): Provides specific logic for how ADR and RQ lines are decoded to select Storage Modules and core locations in 4-way, 2-way, and no-interleave modes, including rules for memory system configuration.
• Controller Operation (Detailed): Explains the state machine and logic flow for starting memory operations, generating acknowledgements, managing data transfer (write strobes, read enables), handling termination and restart based on request status, and detailing the internal core cycle timing signals.
• Storage Module Operation (Detailed): Describes the physical core array (ferrite cores, 3-wire, 256x128 array per mat), the basic core read/write mechanisms (half-select and coincident currents, hysteresis loops, bow-tie winding for noise cancellation), the X-Y selection circuitry (drivers, switches, current generators), and the data buffering and sense/inhibit functions (sense amplifiers, data registers, inhibit drivers). It explains how these components work together during core read and write cycles.

3. Logic Description (Circuit Level):

• This section provides the most detailed description of the MB20 at the circuit level, referencing specific Digital Equipment Corporation print sets. It breaks down the logic of the controller (M8568 Control Module and M8565 Timing Module) and the storage module (H224-B Stack Module, G236 Driver Module, G116 Sense/Inhibit Module).
• Controller Logic: Details the implementation of diagnostic cycle control, memory addressing and SM selection (using latches, mixers, and comparators), start/restart control (including busy logic), ACKN generation, read/write control signals, error detection and flagging, margin control mechanisms, and reset logic.
• Storage Module Logic: Describes the circuitry for stack selection, address decoding (selecting specific X-Y drivers/switches), X-Y drive control (current generation, timing), the drivers and switches themselves, bias current generation, stack charge circuits, inhibit drivers, sense amplifiers, sense strobe control, data registers (flip-flops for data storage), and bias current detection/SM reset logic.

In essence, the MB20 is a sophisticated core memory system for the KL10, designed for high-speed operation through parallel access via interleaving, with robust error checking and extensive diagnostic capabilities.