M7850 Parity Controller Maintenance Manual

This document is the M7850 Parity Controller Maintenance Manual for PDP-11 systems, published in February 1977.

The M7850 Parity Controller is a double-height module designed to increase confidence in data integrity within PDP-11 memory. It achieves this by:

• Parity Generation: When data is written to memory (DATO), the M7850 generates ODD parity bits (P0 for even byte, P1 for odd byte) based on the data, and these parity bits are stored alongside the data in memory. A specific bit in the M7850's Control and Status Register (CSR) allows for diagnostic generation of "wrong" (even) parity.
• Parity Checking: When data is retrieved from memory (DATI), the M7850 recalculates the parity of the incoming data and compares it to the stored parity bits. If they don't match, a parity error is detected, indicating unreliable data.

Key Features and Operations:

• System Integration: One M7850 module is required per backplane containing parity memory modules, handling parity for all memory modules (4K to 96K bytes). It communicates with the PDP-11 system via the Unibus and with memory modules via an internal bus within the backplane.
• Control and Status Register (CSR): The M7850 contains a CSR that has its own Unibus address. This register stores information in case of a parity error (e.g., the high-order bits of the faulty memory address) and contains control bits (e.g., to enable parity error warnings or generate wrong parity for diagnostics).

• Reaction to Parity Errors: If a parity error is detected, the M7850:

  • Sets a flag bit (Bit 15) in its CSR.
  • Records a partial address of the faulty data in the CSR.
  • Activates an LED indicator on the module.
  • Optionally asserts the BUS PB (Parity Bus) signal to warn the processor, if enabled by a CSR bit (Bit 0).
  • Delays the assertion of the BUS SSYN signal, allowing time for error logging.

• Limitations: The parity check cannot detect errors where an even number of bits in a data byte change state, as the parity would remain correct.

Maintenance and Troubleshooting:

• The manual provides instructions for installation, including setting the unique CSR address using jumpers and the crucial step of timing adjustment for the SSYN DLY (0) H signal (110 ns ± 10 ns delay), which is vital for accurate parity error sampling and proper BUS SSYN assertion.
• It outlines the use of diagnostic programs (e.g., MAINDEC-11-DCMFA-C-D) and SCOPE LOOP programs to test the M7850's functionality, generate and check parity, and identify faults. It includes warnings about disabling error indication and clearing wrong-parity generation bits in the CSR during testing.
• A troubleshooting chart and pin-out descriptions are provided to aid in diagnosing common failures.

In essence, the document is a comprehensive guide for understanding the M7850's role in memory integrity, its functional principles, and the practical steps for its installation, configuration, and repair.