KN210 CPU Module Set Technical Manual

This document is the KN210 CPU Module Set Technical Manual (Order Number EK-KN210-TM-001), published by Digital Equipment Corporation in June 1989.

The manual provides comprehensive technical information about the KN210 CPU Module Set, which consists of a KN210 processor module and a KN210 I/O module. These are quad-height modules designed for the Q22-bus (extended LSI-11 bus), intended for high-speed multi-user and multitasking environments, specifically used in the DECsystem 5400.

Key aspects covered include:

• Hardware Architecture:

  • R3000 RISC Processor: The central 32-bit CPU, including its on-chip cache control, memory management (TLB), and a tightly-coupled R3010 Floating-Point Accelerator (FPA).
  • Memory System: Two separate 64 Kbyte instruction and data caches, and a CMCTL memory controller supporting up to 64 Mbytes of ECC memory using MS650-BA/AA memory modules.
  • Interfaces: Detailed descriptions of the Q22-bus interface (CQBIC chip) for main memory and I/O (including address translation via map registers and caching), the DSSI (Digital Small Storage Interconnect) bus interface (SII chip) for mass storage devices, and the Ethernet interface (LANCE chip) for network connectivity.
  • System Support Functions: Provided by the SSC chip, including console serial line, time-of-year clock, programmable timers, battery-backed RAM, and diagnostic LEDs.

• Installation and Configuration: Guidance on installing the KN210 module set and MS650 memory modules in BA213 backplanes, and configuring parameters via the H3602-SA CPU cover panel. Connector pinouts are also detailed.

• Firmware: Description of the 256 Kbytes of ROM-resident firmware, which manages:

  • Power-up self-tests and diagnostics.
  • Console emulation for VAX standard console commands, including an interactive command language for examining and altering processor state.
  • Operating system bootstrapping from various devices (DSSI, MSCP disks, TMSCP tapes, and Ethernet via MOP protocol).
  • Error reporting and halt procedures.

• Diagnostic Processor: Details on the CVAX diagnostic processor, its state, data types, instruction set, memory management, exceptions, and interrupts.

The manual is aimed at design engineers and application programmers familiar with Digital's Q22-bus and MIPS instruction set, serving as a comprehensive programmer's reference.