MicroVAX I

This document, "MicroVAX I CPU Technical Description (Second Edition - August 1984)," provides a comprehensive technical overview and detailed descriptions of the Central Processing Units (CPUs) used in the MicroVAX I system, specifically the KD32-AA and KD32-AB models. It is intended as a field reference for Digital Equipment Corporation (DEC) personnel and for educational training programs, assuming prior knowledge of VAX architecture.

The manual is structured to progressively detail the system, starting from a high-level overview and delving into the intricate microcode and hardware operations of the CPU. Key areas covered include:

• System Introduction (Chapter 1): Provides an overview of the MicroVAX I system, including its architecture (32-bit, microprogrammed, VAX-11 instruction set), major components (the CPU, Q22 bus, various disk drives, memory), physical assembly (front/rear panels, backplane, power supply), and system timing. It notes that the KD32-AA and KD32-AB CPUs differ in their floating-point instruction support.
• Programming Interface (Chapter 2): Describes the software-accessible aspects of the CPU, such as its physical address space (8 megabytes total, split between memory and I/O), virtual-to-physical address translation, internal processor registers (IPRs) like the Interval Clock Control/Status Register and Cache Disable Register, and console terminal registers. A significant portion details the system bootstrap process, including various booting methods (from disk, PROM, Ethernet) and the Microverify diagnostic self-test, which indicates CPU health and errors via LEDs and console messages. It also covers interrupts and exceptions, detailing their types and the System Control Block.
• Processor Configuration (Chapter 3): Focuses on the physical configuration of the KD32-AA and KD32-AB processors, explaining the function and setting of option switches for baud rate, break detection, system recovery actions (warm start, boot, halt), and bootstrap search order. Power and cooling specifications for the CPU modules are also provided.
• Functional Overview (Chapter 4): Introduces the CPU's operation at a microprogram level, outlining the roles of the Data Path Module (DAP) and Memory Controller Module (MCT). It describes the main components of each module (e.g., ALU, control store, cache, translation buffer) and illustrates the flow of data through the system using examples of macroinstruction execution (e.g., prefetch, Move Byte, Subtract One and Branch).

• Detailed Microcode and Hardware Descriptions (Chapters 5-9): These chapters provide in-depth "theory of operation":

  • Data Path Microcode (Chapter 5): Explains the format and functions of the DAP's 40-bit microinstructions, including control fields for condition codes, data path operations, and next microaddress generation.
  • Data Path Module (Chapter 6): Describes the hardware components of the DAP module responsible for controlling microinstruction flow, decoding macroinstructions, executing microinstructions, transferring data internally and to external devices, processing interrupts, and communicating with the console terminal and memory controller.
  • Memory Controller Microcode (Chapter 7): Details the MCT's 64-bit microinstruction format and the parameters it uses to perform memory functions, including controlling the Q22 bus interface, functional blocks within the memory controller, and its internal microprogram flow.
  • Memory Controller Module (Chapter 8): Explains the hardware of the MCT module, covering clock generation, microinstruction flow control, virtual address translation (Translation Buffer and Cache), data transfer paths (MCA/MCD buses), instruction prefetching, and status tracking/reporting. It includes a step-by-step example of a Move Word (MOVW) instruction's execution.
  • Q22 Bus Controller (Chapter 9): Describes the hardware and protocols of the Q22 bus controller, detailing its functions in servicing memory controller requests, sequencing bus cycles (reads, writes, block transfers), arbitrating bus mastership, handling bus errors (parity, timeouts), and monitoring Direct Memory Access (DMA) for cache invalidation.

• Appendices: Provide essential reference information, including detailed Q22 bus signals, module pin assignments, serial line cable pinning, a comprehensive guide to the Microverify diagnostic, and a complete listing of the MicroVAX instruction set.

In summary, this manual serves as an exhaustive technical reference for understanding the MicroVAX I CPU, from its overall system context and programmer-visible interfaces down to its internal microcode logic, hardware components, and bus communication protocols.