Addendum to KA680 CPU Module Technical Manual

This document is an addendum to the KA680 CPU Module Technical Manual, expanding its coverage to include information for the KA675, KA681, KA690, KA691, and KA692 CPU modules.

It provides comprehensive updates and additions to the original manual, detailing the key differences and specifications across these CPU models. Key areas of change include:

• Hardware Specifications: Outlines variations in clock speed, cache sizes (128 KB, 512 KB, 2 MB), and I/O expansion capabilities for each CPU module, along with updated block diagrams and component descriptions.
• Cache Architecture: Details the 3-level cache hierarchy (VIC, Pcache, Bcache), specifying model-specific cache sizes, addressing schemes, and configuration, noting the absence of the Virtual Instruction Cache (VIC) in the KA675.
• I/O and Bus Interfaces: Provides information on DSSI expansion for specific modules (KA681, KA691, KA692) via a dual-DSSI daughter card, updates System Control Block entries, and revises CP bus cycle times and SHAC register details.
• System Registers & Configuration: Offers extensive updates to system control and diagnostic registers (e.g., MMCDSR, ICSR, CCTL), including model-specific values, timings, memory refresh intervals, and the configurable machine states after power-up ROM diagnostics.
• Console Commands: Introduces new console commands such as LOGIN, SET DSSI_ID, SET PSE (secure console mode), SET PSWD, and SHOW SAVED_STATE for system security and configuration.
• Operational Details: Includes updated power consumption figures and system identification information for all covered modules.

Unless explicitly stated otherwise, all references to the KA680 CPU module in the original manual are now considered applicable to the KA675, KA681, KA690, KA691, and KA692 CPU modules as well.